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參數資料
| 型號： | Q67040-S4124-A2 |
| 廠商： | SIEMENS AG |
| 英文描述： | SIPMOS Power Transistor |
| 中文描述： | SIPMOS功率晶體管 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 139K |
| 代理商： | Q67040-S4124-A2 |
Semiconductor Group
3
29/Jan/1998
SPD13N05L
SPU13N05
L
Electrical Characteristics,
at
T
j
= 25°C, unless otherwise specified
Parameter
Symbol
Values
Unit
min.
typ.
max.
Dynamic Characteristics
Transconductance
V
DS
≥
2
*
I
D *
R
DS(on)max,
I
D
= 8.8 A
Input capacitance
g
fs
5
8
-
S
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Output capacitance
C
iss
-
317
400
pF
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Reverse transfer capacitance
C
oss
-
97
120
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Turn-on delay time
C
rss
-
54
70
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 12.5 A
R
G
= 16
Rise time
t
d(on)
-
15
22
ns
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 12.5 A
R
G
= 16
Turn-off delay time
t
r
-
106
160
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 12.5 A
R
G
= 16
Fall time
t
d(off)
-
11
17
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 12.5 A
R
G
= 16
Gate charge at threshold
t
f
-
14
20
V
DD
= 40 V,
I
D
≥
0.1 A,
V
GS
=0 to 1 V
Gate charge at 5.0 V
Q
g(th)
-
0.37
0.56
nC
V
DD
= 40 V,
I
D
= 12.5 A,
V
GS
=0 to 5 V
Gate charge total
Q
g(5)
-
7.85
12
V
DD
= 40 V,
I
D
= 12.5 A,
V
GS
=0 to 10 V
Gate plateau voltage
Q
g(total)
-
13.5
20
V
DD
= 40 V,
I
D
= 12.5 A
V
(plateau)
-
4
-
V
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| Q67040-S4136 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:SIPMOS PowerTransistor |
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