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參數(shù)資料
型號： Q67107-H5167-A703
廠商： SIEMENS AG
英文描述： DDC-PLUS-Deflection Controller
中文描述： DDC的加偏轉控制器
文件頁數(shù)： 17/47頁
文件大小： 237K
代理商： Q67107-H5167-A703
SDA 9361
Semiconductor Group
17
1998-02-01
2.5.3
I
2
C-Bus Commands
1)
see 2.5.5: Explanation of some control items
Control item
S
aD7 D6 D5 D4 D3 D2 D1 D0 Allowed
00
H
see below
01
H
see below
02
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
03
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
04
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
05
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
06
H
B7 B6 B5 B4 B3 B2 B1 B0
Range
Effective
Range
Can be
Disabled
by Bit
–
–
–
–
–
–
–
Default
Value if
Disabled
–
–
–
–
–
–
–
Unit
Deflection control 0
Deflection control 1
Vertical shift
Vertical size
Vertical linearity
Vertical S-correction
Vertical EHT
compensation
1)
Horizontal size
Pin phase
Pin amp
Upper corner pin
correction
Lower corner pin
correction
Horizontal EHT
compensation
1)
Horizontal shift
Vertical angle
Vertical bow
PWM start
D/A
1)
Vertical blanking time
1)
Horizontal blanking time
Start vertical scan
1)
Horizontal blanking
phase
Vertical scan width 0
1)
Vertical scan width 1
1)
Guard band
1)
Start reduced scan
1)
–
–
–
–
–
–
–
–
–
–
–
0..255
0..255
07
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
08
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
09
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
0A
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
–
–
–
–
–
–
–
–
–
–
–
–
0B
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
–
–
–
0C
H
B7 B6 B5 B4 B3 B2 B1 B0
0..255
0..255
–
–
–
0D
H
B6 B5 B4 B3 B2 B1 B0 X
0E
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
0F
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127
10
H
B7 B6 B5 B4 B3 B2 B1 B0
11
H
B5 B4 B3 B2 B1 B0 X
12
H
X B6 B5 B4 B3 B2 B1 B0
13
H
X
X
B5 B4 B3 B2 B1 B0
14
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127
15
H
B5 B4 B3 B2 B1 B0
-64..63
-64..63
–
–
–
–
–
–
–
–
–
–
b)
1/CLL
–
–
4/CLL
–
lines
4/CLL
line
4/CLL
0..255
-32..31
0..127
0..63
0..215
-32..31
a)
0..63
c)
-32..31
X
BSE = 0
BSE = 0 H-flyback
SSE = 0
–
9
–
-32..31
15
H
16
H
B7 B6 B5 B4 B3 B2 B1 B0
17
H
X
X
B5 B4 B3 B2 B1 B0
18
H
X
X
B5 B4 B3 B2 B1 B0
B9 B8
0..+3
0..255
0..63
0..63
d)
d)
STE = 0
STE = 0
GBE = 0
SRSE =
0
–
–
–
–
e)
e)
3
2
256 lines
lines
half lines
line
0..63
0, 2..63
Vertical sync control
Min. No. of lines / field
1)
1A
H
B7 B6 B5 B4 B3 B2 B1 B0
Max. No. of lines / field
1)
1B
H
B7 B6 B5 B4 B3 B2 B1 B0
AFC EHT
compensation
1)
Internal PLL control
1D
H
Internal H-sync phase
1E
H
B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -96..119
PWM width
1F
H
B7 B6 B5 B4 B3 B2 B1 B0
19
H
see below
–
–
–
–
–
–
–
0..255
0..255
-32..31
0..255
0..255
-32..31
2 lines
2 lines
–
1C
H
B5 B4 B3 B2 B1 B0 X
X
see below
–
–
–
–
–
–
15
–
4/CLL
4/CLL
0..255
0..215
PWM
width=0
–
–
–
Universal register 1
Universal register 3
Internal voltage Ref
control
45
H
47
H
48
H
see below
see below
see below
–
–
–
–
–
–
–
–
–
–
–
–
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