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參數資料
| 型號： | Q67121C452 |
| 英文描述： | IC-SM-8-BIT CPU-12MHZ |
| 中文描述： | 集成電路釤8位CPU - 12MHz的 |
| 文件頁數： | 47/121頁 |
| 文件大小： | 1000K |
| 代理商： | Q67121C452 |
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Semiconductor Group
6-13
On-Chip Peripheral Components
C501
6.2
Timers/Counters
The C501 contains three 16-bit timers/counters, timer 0, 1, and 2, which are useful in many
applications for timing and counting.
In “timer” function, the timer register is incremented every machine cycle. Thus one can think of it
as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the counter
rate is 1/12 of the oscillator frequency.
In “counter” function, the timer register is incremented in response to a 1-to-0 transition (falling
edge) at its corresponding external input pin, T0, T1, or T2 (alternate functions of P3.4, P3.5 and
P1.0 resp.). In this function the external input is sampled during S5P2 of every machine cycle. When
the samples show a high in one cycle and a low in the next cycle, the count is incremented. The
new count value appears in the register during S3P1 of the cycle following the one in which the
transition was detected. Since it takes two machine cycles (24 oscillator periods) to recognize a 1-
to-0 transition, the maximum count rate is 124 of the oscillator frequency. There are no restrictions
on the duty cycle of the external input signal, but to ensure that a given level is sampled at least
once before it changes, it must be held for at least one full machine cycle.
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