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參數資料
型號: Q67121C452
英文描述: IC-SM-8-BIT CPU-12MHZ
中文描述: 集成電路釤8位CPU - 12MHz的
文件頁數: 83/121頁
文件大?。?/td> 1000K
代理商: Q67121C452
Interrupt System
C501
Semiconductor Group
7-5
The
timer 2 interrupt
is generated by the logical OR of bit TF2 and EXF2 in register T2CON.
Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and
the bit will have to be cleared by software.
The
serial port interrupt
is generated by a logical OR of flag RI and TI in SFR SCON. Neither of
these flags is cleared by hardware when the service routine is vectored too. In fact, the service
routine will normally have to determine whether it was the receive interrupt flag or the transmission
interrupt flag that generated the interrupt, and the bit will have to be cleared by software.
Special Function Register T2CON (Address C8H)
Special Function Register SCON (Address. 98H)
Reset Value : 00H
Reset Value : 00H
The shaded bits are not used for interrupt request control.
Bit
Function
TF2
Timer 2 Overflow Flag.
Set by a timer 2 overflow. Must be cleared by software. TF2 will not be set when
either RCLK = 1 or TCLK = 1.
EXF2
Timer 2 External Flag.
Set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to
vector to the timer 2 interrupt routine. EXF2 must be cleared by software. EXF2
does not cause an interrupt in up/down counter mode (DCEN = 1, SFR T2MOD)
TI
Serial interface transmitter interrupt flag
Set by hardware at the end of a serial data transmission. Must be cleared by
software.
RI
Serial interface receiver interrupt flag
Set by hardware if a serial data byte has been received. Must be cleared by
software.
TF2
EXF2
RCLK
TCLK
C8H
T2CON
EXEN2
TR2
C/T2
CP/RL2
Bit No.
CF
H
MSB
LSB
C8
H
CE
H
CD
H
CC
H
CB
H
CA
H
C9
H
SM0
SM1
SM2
REN
98H
SCON
Bit No.
9F
H
TB8
RB8
TI
RI
9E
H
9D
H
9C
H
9B
H
9A
H
99
H
98
H
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