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參數(shù)資料
| 型號： | QL5064-75CPB484C |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 1/37頁 |
| 文件大小： | 806K |
| 代理商： | QL5064-75CPB484C |
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QL5064 QuickPCI Data Sheet Rev D
1
QL5064 QuickPCI Data Sheet
66 MHz/64-bit PCI Master/Target with Embedded Programmable
Logic and dual Port SRAM
1.0 Device Highlights
High Performance PCI Controller
64-bit / 66 MHz Master/Target PCI
Controller (automatically backwards
compatible to 33 MHz or/and 32-bits)
75 MHz PCI Interface supported for
embedded systems
PCI Specification v2.2 compliance
Programmable back-end interface with three
64-bit busses/100 MHz
Provides full 533 MB/s PCI data transfer
rates (600 MB/s at 75 MHz)
Advanced PCI Features
DMA Chaining mode for queued DMA
transactions
Four-channel DMA mastering, plus a SPCI
(Single PCI Access) mode
Unlimited bursts supported in Master and
Target mode
Two Master Write FIFOs and two Master
Read FIFOs, each 64-deep and 64 bits wide
Target Read and Write FIFOs for pre-fetched
reads and multipleposted writes
Programmable interrupt controller
I2O compliant under microprocessor control
16 Mailbox registers for message passing and
semaphores
Extended configuration space allowing
Messaged Interrupts,
power management, and future PCI
enhancement support
Extremely Flexible and Configurable
Supports processor-less systems, as well as 0
wait-state burst connections to all known
8/16/32/64 bit processors
Includes non-volatile on-chip configuration
data for total customization
Independent PCI bus (66 MHz) and local bus
(100 MHz) clocks
All local interface, control, and glue-logic can
be implemented on chip
“PCI friendly” pinout simplifies board layout,
supports 4-layer PCI boards
Advanced Master DMA Features
Programmable DMA Channel Arbitration
Scheme
SPCI (Single PCI Access) mode may initiate
any PCI Master command
DMA controller configurable via PCI or
back-end
DMA Chaining mode allows a linked list of
DMA transfers to occur without user
intervention
High Performance PCI Target
Write posting FIFO increases performance
with queued transactions
(up to 16 queued writes)
Any BAR can be defined as pre-fetchable
Six base address registers supported,
configurable as memory or IO
Unique “Target Blast Mode” enables high-
performance and very low overhead
streaming data to/from PCI
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