- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376314 > RM7000-263S (PMC-Sierra, Inc.) RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released PDF資料下載
參數(shù)資料
| 型號： | RM7000-263S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數(shù)據(jù)發(fā)布 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7000-263S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
26
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 6 Cache Attributes
Attribute
Size
4.22 Cache Locking
The RM7000 allows critical code or data fragments to be locked into the primary and secondary
caches. The user has complete control over what locking is performed with cache line granularity.
For instruction and data fragments in the primaries, locking is accomplished by setting either or
both of the cache lock enable bits in the CP0 ECC register, specifying the set via a field in the CP0
ECC register, and then executing either a load instruction or a Fill_I cache operation for data or
instructions respectively. Only two sets are lockable within each cache: set A and set B. Locking
within the secondary works identically to the primaries using a separate secondary lock enable bit
and the same set selection field. As with the primaries, only two sets are lockable: sets A and B.
Table 7 summarizes the cache locking capabilities.
Table 7 Cache Locking Control
Cache
Lock Enable
Primary I
ECC[27]
4.23 Cache Management
To improve the performance of critical data movement operations in the embedded environment,
the RM7000 significantly improves the speed of operation of certain critical cache management
Instruction
16KB
Data
16KB
Secondary
256KB
Tertiary
512K, 1M, 2M, 4M,
or 8M
direct mapped
direct replacement
Associativity
Replacement
Algorithm.
Line size
Index
4-way
cyclic
4-way
cyclic
4-way
cyclic
32 byte
vAddr
11..0
pAddr
35..12
n.a.
32 byte
vAddr
11..0
pAddr
35..12
write-back, write-
through
non-blocking (2
outstanding)
critical word first
sequential
first double (if
waiting for data)
per byte
32 byte
pAddr
15..0
pAddr
35..16
block write-back,
bypass
non-blocking (data
only, 2 outstanding)
critical word first
sequential
n.a.
32 byte
pAddr
22..0
pAddr
35..19
block write-through,
bypass
non-blocking (data
only, 2 outstanding)
critical word first
sequential
n.a.
Tag
Write policy
read policy
n.a.
read order
write order
miss restart
following:
Parity
critical word first
NA
complete line
per word
per doubleword
per byte
Set Select
ECC[28]=0
→
A
ECC[28]=1
→
B
ECC[28]=0
→
A
ECC[28]=1
→
B
ECC[28]=0
→
A
ECC[28]=1
→
B
Activate
Fill_I
Primary D
ECC[26]
Load/Store
Secondary
ECC[25]
Fill_I or
Load/Store
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM7000-266T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7935 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RM7965 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM7000-266T | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。