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參數資料
| 型號： | RM7000-300T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 300 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數： | 33/54頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7000-300T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
33
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 9 Watch Control Register
Register
Bit Field/Function
63
Watch1, 2
Store
31:2
Watch Mask
Mask
4.34 Performance Counters
Like the Test/Break-point capability described above, the Performance Counter feature has been
added to improve the observability and controllability of the processor thereby easing system
debug and, especially in the case of the performance counters, easing system tuning.
The Performance Counter feature is implemented using two new CP0 registers, PerfCount and
PerfControl. The PerfCount register is a 32-bit writable counter which causes an interrupt when bit
31 is set. The PerfControl register is a 32-bit register containing a five bit field which selects one
of twenty-two event types as well as a handful of bits which control the overall counting function.
Note that only one event type can be counted at a time and that counting can occur for user code,
kernel code, or both. The event types and control bits are listed in Table 10.
62
Load
61
Instr
60:36
0
35:2
Addr
1
Mask
Watch
2
1:0
0
0
Mask
Watch
1
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相關代理商/技術參數 |
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|---|---|
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
| RM7000A-350T | 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A-350TI | 制造商:PMC 制造商全稱:PMC 功能描述:RM7000Aa?￠ Microprocessor with On-Chip Secondary Cache Data Sheet Released |
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