- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376314 > RM7000-300T (PMC-SIERRA INC) RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released PDF資料下載
參數(shù)資料
| 型號(hào)： | RM7000-300T |
| 廠商： | PMC-SIERRA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 300 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁(yè)數(shù)： | 48/54頁(yè) |
| 文件大小： | 901K |
| 代理商： | RM7000-300T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)當(dāng)前第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
48
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
10.3 System Interface Parameters
10.4 Boot-Time Interface Parameters
Parameter
1
Data Output
2,3
t
DO
Symbol Test Conditions
mode14..13 = 10 (fastest) 1.0
mode14..13 = 11
mode14..13 = 00
mode14..13 = 01
(slowest)
t
DS
t
rise
= see above table
t
fall
= see above table
t
DH
CPU Speed
200 MHz
Min Max
5.0
1.0
5.5
1.0
6.0
1.0
7.0
Units
ns
ns
ns
ns
250 MHz
Min
1.0
1.0
1.0
1.0
266 MHz
Min
1.0
1.0
1.0
1.0
300 MHz
Min
1.0
1.0
1.0
1.0
Max
5.0
5.5
6.0
6.5
Max
4.5
5.0
5.0
6.0
Max
4.5
4.5
5.0
5.5
Data Setup
4
2.5
2.5
2.5
2.5
ns
Data Hold
4
Notes
1.0
1.0
1.0
1.0
ns
1. Timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O.
2. Capacitive load for all output timings is 50 pF.
3. Data Output timing applies to all signal pins whether tristate I/O or output only.
4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5. Only mode 14:13 = 10 is tested and guaranteed.
Parameter
7
Mode Data
Setup
Mode Data Hold t
DH
Symbol
t
DS
Test Condi-
tions
Min
4
Max
Units
SysClock cycles
0
SysClock cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM7935 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RM7965 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RMLA3565-58 | Wideband Low Noise MMIC Amplifier |
| RMLA3565A-58 | Wideband Low Noise MMIC Amplifier |
| RN1102 | Isolated Resistor Termination Network |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM7000A | 制造商:PMC 制造商全稱(chēng):PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
| RM7000A-350T | 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A-350TI | 制造商:PMC 制造商全稱(chēng):PMC 功能描述:RM7000Aa?￠ Microprocessor with On-Chip Secondary Cache Data Sheet Released |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。