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參數(shù)資料
| 型號(hào)： | S2004 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器) |
| 中文描述： | 四串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器） |
| 文件頁(yè)數(shù)： | 1/38頁(yè) |
| 文件大?。?/td> | 377K |
| 代理商： | S2004 |
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1
S2004
S2004
QUAD SERIAL BACKPLANE DEVICE
October 10, 2000 / Revision D
DEVICE
SPECIFICATION
MAC
(ASIC)
S2004
QUAD
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
TO SERIAL BACKPLANE
S2204
GE INTERFACE
SERIAL BP DRIVER
Figure 1. Typical Quad Gigabit Ethernet Application
FEATURES
Broad operating rate range (.98 - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
Quad Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
Quad Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
On-chip 8B/10B line encoding and decoding for
four separate parallel 8-bit channels
32-bit parallel TTL interface with internal series
terminated outputs
Low-jitter serial PECL interface
Individual local loopback control
JTAG 1149.1 Boundary scan on low speed I/O
signals
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 2.5 W power dissipation
Compact 23mm x 23mm 208 TBGA package
APPLICATIONS
Ethernet Backbones
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2004 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides four
separate transceivers which can be operated indi-
vidually or locked together for an aggregate data ca-
pacity of >4 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip quad
receive PLL is used for clock recovery and data re-
timing on the four independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a 3.3V power supply and dissi-
pates 2.5 watts.
Figure 1 shows the S2004 and S2204 in a Gigabit
Ethernet application. Figure 2 combines the S2004
with a crosspoint switch to demonstrate a serial
backplane application. Figure 3 is the input/output
diagram. Figures 4 and 5 show the transmit and
receive block diagrams, respectively.
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