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參數(shù)資料
| 型號(hào)： | S2058 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器) |
| 中文描述： | 繞道和中繼端口的光纖通道仲裁環(huán)路（用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器） |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 136K |
| 代理商： | S2058 |
1
S2058
S2058
PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP
PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP
FEATURES
ANSI X3T11 Fibre Channel Compatible
Monolithic Clock Recovery Unit
– Re-times & Buffers Received Data
– Jitter Peaking < 0.15 dB
Lock Detect Function
– Run Length Violation Detector
– Frequency Detection
Port Bypass Circuit
Suitable for both Coaxial and Optical Link
APPLICATIONS
Low Power Operation 0.425W, Typical
106.25 or 53.125 MHz Reference Clock
28-Pin SOIC Package
3.3V Supply
GENERAL DESCRIPTION
The Fibre Channel Port Bypass with Repeater Cir-
cuit is used in full-speed (1.0625 Gb/s) Disk Arrays.
The S2058 block diagram is shown in Figure 1. It
contains a monolithic Clock Recovery Unit (CRU), a
lock detect feature and a port bypass Circuit. The
CRU may be used alone to implement a general
purpose Repeater needed for many Disk Array and
Switch applications where a re-timed and buffered
signal is required. The S2058 may be used to imple-
ment a single chip Arbitrated Loop Port Bypass Re-
timing Node. The S2058 performs the function of a
port bypass circuit followed by a clock and data
retiming Phase Locked Loop (CDR). The CDR re-
times incoming serial data, detects whether a valid
signal is present and outputs a low jitter serial data
stream.
FUNCTIONAL DESCRIPTION
The S2058 performs two functions. The first is a Port
Bypass Circuit (PBC) for nodes in a FC-AL system.
The low jitter accumulation of the Port Bypass Path
is essential in these systems. The second function is
to retime and restore signal quality in RAID drives
using the FC-AL link configuration. The low jitter
transfer peaking and the high jitter tolerance specifi-
cations of the Clock and Data Recovery PLL are
essential in these applications. In addition, the Lock
Figure 1. S2058 Block Diagram
detect circuit monitors the incoming signals for valid
8B/10B run length, transition density and frequency.
The output of this circuit is useful for link perfor-
mance monitoring and detection of channel present.
Jitter Performance
The S2058 complies with the minimum jitter toler-
ance requirements proposed by the Fibre Channel
jitter working group when used with differential in-
puts and outputs as shown in Figure 2. In addition,
the S2058 is designed for minimum jitter generation
and jitter transfer specifications. This allows the opti-
mum system design for arbitrated loop architectures.
Jitter Tolerance
Input jitter tolerance is defined as the amplitude of
frequency dependent, random and deterministic jitter
that causes the clock recovery PLL to violate the
BER specifications. Input jitter tolerance specifica-
tions are shown in Figures 3 and 4.
CDR
normal
0
1
S2058
LCKREFN
REFCLK
LOCKDET
TEST
SEL
DDI P/N
DDO P/N
IN P/N
OUT P/N
LPF1
LPF2
REFSEL
24
2.2
μ
F (X7R Type)
24
DEVICE
SPECIFICATION
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