- 您現在的位置：買賣IC網 > PDF目錄192296 > S29CD032J1JFFN020 (SPANSION LLC) 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80 PDF資料下載
參數資料
| 型號： | S29CD032J1JFFN020 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數： | 78/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CD032J1JFFN020 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當前第78頁
September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
7
Pr el im i n a r y
2
Input/Output Descriptions and Logic Symbols
Table identifies the input and output package connections provided on the device.
Symbol
Type
Description
A19-A0
Input
Address lines for S29CD-J and S29CL-J (A18-A0 for 16Mb and A19-A0 for 32Mb).
A9 supports 12V autoselect input.
DQ31-DQ0
I/O
Data input/output
CE#
Input
Chip Enable.
This signal is asynchronous relative to CLK for the burst mode.
OE#
Input
Output Enable.
This signal is asynchronous relative to CLK for the burst mode.
WE#
Input
Write Enable
VCC
Supply
Device Power Supply.
This signal is asynchronous relative to CLK for the burst mode.
VIO
Input
VersatileI/OTM Input.
VSS
I/O
Ground
NC
No Connect
Not connected internally
RY/BY#
Output
Ready/Busy output and open drain which require a external pull up resistor.
When RY/BY# = VOH, the device is ready to accept read operations and commands.
When RY/BY# = VOL, the device is either executing an embedded algorithm or the
device is executing a hardware reset operation.
CLK
Input
Clock Input that can be tied to the system or microprocessor clock and provides the
fundamental timing and internal operating frequency.
AVD #
Input
Load Burst Address input.
Indicates that the valid address is present on the address inputs.
IND#
Output
End of burst indicator for finite bursts only.
IND is low when the last word in the burst sequence is at the data outputs.
WAIT#
Output
Provides data valid feedback only when the burst length is set to continuous.
WP#
Input
Write Protect Input.
At VIL, disables program and erase functions in two outermost sectors of the large
bank.
ACC
Input
Acceleration input.
At VHH, accelerates erasing and programming.
When not used for acceleration, ACC = VSS to VCC.
RESET#
Input
Hardware Reset.
相關PDF資料 |
PDF描述 |
|---|---|
| S29CL032J0RFAI113 | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| S29CL032J0RFAN130 | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| S29CL032J0RFFI110 | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| S29CL032J0RFFN130 | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| S29CL032J1JFAI110 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| S29CL016J0JQFM030 | 制造商:Spansion 功能描述:FLASH PARALLEL 3.3V 16MBIT 512KX32 54NS 80PQFP - Trays |
| S29CL016J0JQFM030P | 制造商:Spansion 功能描述:AUTO 3.3V 512KX32 FLASH - Trays |
| S29CL016J0JQFM030U | 制造商:Spansion 功能描述:32M (4MX8/2MX16) 3V REG, MIRRORBIT, TOP, FBGA48, IND - Trays |
| S29CL016J0JQFM03U | 制造商:Spansion 功能描述:32M (4MX8/2MX16) 3V REG, MIRRORBIT, TOP, FBGA48, IND - Trays |
| S29CL016J0MQFM030 | 制造商:Spansion 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。