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參數資料
型號: S29CL032J1MFAN120
廠商: SPANSION LLC
元件分類: PROM
英文描述: 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
封裝: 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80
文件頁數: 31/78頁
文件大小: 1825K
代理商: S29CL032J1MFAN120
September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
35
Pr el im i n a r y
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector
selected for erasure. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5
Figure 8.7 Data# Polling Algorithm
8.8.2
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress
or complete, or whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of
the final WE# pulse in the command sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, two immediate consecutive read cy-
cles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchro-
nous mode, the rising edge of ADV# is used or the rising edge of clock while ADV# is Low.
DQ7 = Data?
Yes
No
DQ5 = 1?
No
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
相關PDF資料
PDF描述
S29CL032J0PQAN102 1M X 32 FLASH 3.3V PROM, 54 ns, PQFP80
S29GL016A10FAI020 1M X 16 FLASH 3V PROM, 100 ns, PBGA64
S29GL032A10TAIR10 64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY
S29GL032A10TAIR12 64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY
S29GL032A10TAIR13 64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY
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