
1
S3045
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
March 12, 2001 / Revision F
FEATURES
Complies with Bellcore and ITU-T
specifications
Supports STS-12/STM-4 to STS-48/STM-16
Mux/Demux functions
8-bit LVDS data path for STS-48/STM-16 data
8-bit LVTTL data path with parity for each
STS-12/STM-4 data stream
Optionally calculates even or odd parity over
parallel data bus or data and frame pulse
Compatible with AMCC S3041/S3042 Mux/
Demux chipset
Compatible with PMC PM5355 User Network
Interface device and PMC PM5312 STTX
Optionally calculates and inserts Byte
Interleaved Parity (B1)
Optionally compares B1 Byte Interleave Parity
on the receive side. Generates and inserts B1
Error indications (B1ERR)
Optionally calculates and inserts M1 Bytes, and
recalculates and inserts the B2 parity bytes
due to the M1 insertions
Optionally inserts section-trace bytes (J0/Z0) in
the transmit path
Diagnostic Loopback Mode
Out of Frame (OOF) monitor and alarm indication
Loss of Signal (LOS) monitor and alarm indication
Squelch Mode: Provides downstream clock
during Clock Recovery Failure
Receive J0 Frame Pulse (J0FP) indicator
Performs optional Frame synchronous
scrambling and descrambling
Provides synchronization signal to STS-12/
STM-4 Network Interface Processors
Single 3.3V supply
5 Volt tolerant input
208-pin PQFP/TEP package
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add drop multiplexers
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
ATM Switch Backbones
GENERAL DESCRIPTION
The S3045 SONET/SDH byte interleave chip is a
fully integrated STS-12/STM-4 to STS-48/STM-16
Mux/Demux device. The S3045 performs all neces-
sary byte interleave and byte de-interleave functions
for multiplexing and de-multiplexing of four STS-12/
STM-4 data streams into/from a single STS-48/STM-
16 data stream. The S3045 functions in conformance
with SONET/SDH transmission standards and is suit-
able for SONET-based ATM applications. Figure 1
shows a typical network application. Byte Interleave
parity (B1) is calculated and inserted for the transmit
path and calculated, compared and inserted for the
receive path. Optional frame synchronous scram-
bling and descrambling are performed, and an
STS-12/STM-4 framing signal is provided to the
STS-12/STM-4 interface processors to allow syn-
chronization of the receive STS-12/STM-4 data
streams.
Figure 1. System Block Diagram
DEVICE
SPECIFICATION
8
ORX
OTX
ORX
OTX
S3041
Tx
S3042
Rx
S3040
CDR
S
4
8
8
8
8
8
8
8
8
8
S3040
CDR
S3042
Rx
S3041
Tx
S
4
8
8
8
8
8
8
8
8
8
8