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S3067
S3067
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC
October 26, 2000 / Revision A
DEVICE
SPECIFICATION
FEATURES
SiGe BiCMOS technology
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLL for clock
generation
Supports OC-48 (with FEC),
OC-24 (with FEC),
OC-12 (with FEC),
OC-3 (with FEC)
FEC capability of up to 8 bytes per
255-byte block
Reference frequency of 155.52 to 178 MHz
Interface to LVPECL and TTL logic
16 Bit single-ended LVPECL data path
Compact 156 TBGA package
Diagnostic loopback mode
Supports line timing
Lock Detect
Signal detect input
Low jitter LVPECL interface
Internal FIFO to decouple transmit clocks
Single 3.3 V supply
Typical power 1.5 W
APPLICATIONS
Wavelength Division Multiplexing equipment
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
Figure 1. System Block Diagram
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
GENERAL DESCRIPTION
The S3067 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization
SONET OC-48, OC-24, OC-12 and OC-3 interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission and
Forward Error Correction (FEC) standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3067
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
155.52 to 178 MHz reference clock, in support of
existing system clocking schemes.
The low jitter LVPECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3067 is packaged in a 156
TBGA, offering designers a small package outline.
The S3067 supports FEC designs with internal divid-
ers or external clocking modes.
S3076
Clock
Recovery
Unit
S3062
Receive
S3062
Transmit
FEC Added
S3067
Transmit
Serialization
S3067
Receive
Deserialization
S3076
Clock
Recovery
Unit
S3062
Receive
FEC Data
Stripped Off
S3062
Transmit
S3067
Transmit
Serialization
S3067
Receive
Deserialization
2.488 Gbps
X
2.488
Gbps
X
155 Mbps
X
2.67 Gbps
X + Y
167 Mbps
X + Y
167 Mbps
X + Y
155 Mbps
X
X + Y
2.67 Gbps
2.488 Gbps
X
PERFORMANCE MONITOR
PERFORMANCE MONITOR
X = Data
Y = FEC Data
E/O
O/E
OPTICAL FIBER