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參數(shù)資料
型號(hào): S4406
廠商: Applied Micro Circuits Corp.
英文描述: 12-Output BiCMOS PLL Clock Generator(能產(chǎn)生12個(gè)時(shí)鐘輸出的BiCMOS鎖相環(huán)時(shí)鐘發(fā)生器)
中文描述: 12路輸出的BiCMOS PLL時(shí)鐘發(fā)生器(能產(chǎn)生12個(gè)時(shí)鐘輸出的BiCMOS工藝鎖相環(huán)時(shí)鐘發(fā)生器)
文件頁數(shù): 1/8頁
文件大小: 106K
代理商: S4406
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page
1
FEATURES
Generates outputs from 10 MHz to 66 MHz
Four groups of three outputs (12 outputs total)
Eight user-selectable output functions for each
group
TTL compatible outputs, with <1.5-ns edge rates
Performs clock doubling, dividing, invert, lead/lag
placement
Internal VCO running between 160 to 266 MHz
1.0
μ
BiCMOS technology
Output skew less than 500 ps
52 PQFP package
APPLICATIONS
High-performance microprocessor systems
CMOS ASIC systems
Backplane clock deskew and distribution
Compatible with Intel’s Pentium processor
GENERAL DESCRIPTION
The S4406 BiCMOS clock generator provides 12 TTL
outputs with less than 500 ps of skew. Implemented
in AMCC’s 1.0
μ
BiCMOS technology, the internal
PLL and divider/delay selector logic allow the user to
individually tailor the (4) TTL output groups to the
system’s needs. The internal VCO can operate be-
tween 160 to 266 MHz, and the programmability al-
lows the user to generate output clocks in the 20–66
MHz range.
The S4406 offers the user the ability to select the
appropriate phase and frequency relationship for
each of the four groups of three TTL clock outputs.
In addition to clock doubling and inversion functions,
the S4406 allows any output groups to lead or lag the
others by the minimum phase delay of 3.75–6.25 ns.
Figure 1. S4406 Block Diagram
PHASE
DETECTOR
CHARGE
PUMP
VCO
I
0
I
1
MUX
REFCLK
FBCLK
TSTEN
0 MS2,1,0
DIVIDE
BY 2 OR 4
DELAY
GENERATION
LOGIC
0 FOUT 0
MODE
SELECTION 1
FILTER
Digital
+5V
0V
Analog
+5V
0V
÷ 2
0 FOUT 1
0 FOUT 2
1 MS2,1,0
1 FOUT 0
MODE
SELECTION 2
1 FOUT 1
1 FOUT 2
2 MS2,1,0
2 FOUT 0
MODE
SELECTION 3
2 FOUT 1
2 FOUT 2
3 MS2,1,0
3 FOUT 0
MODE
SELECTION 4
3 FOUT 1
3 FOUT 2
3
3
3
3
disable
disable
disable
disable
S
DEVICE SPECIFICATION
12-OUTPUT BiCMOS PLL CLOCK GENERATOR
S4406
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