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參數資料
| 型號： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數： | 1/25頁 |
| 文件大小： | 364K |
| 代理商： | SCANPSC100F |
SCANPSC100F
Embedded Boundary Scan Controller
(IEEE 1149.1 Support)
General Description
The SCANPSC100F is designed to interface a generic paral-
lel processor bus to a serial scan test bus. It is useful in im-
proving scan throughput when applying serial vectors to sys-
tem test circuitry and reduces the software overhead that is
associated with applying serial patterns with a parallel pro-
cessor. The ’PSC100F operates by serializing data from the
parallel bus for shifting through the chain of 1149.1 compliant
components (i.e., scan chain). Scan data returning from the
scan chain is placed on the parallel port to be read by the
host processor. Up to two scan chains can be directly con-
trolled with the ’PSC100F via two independent TMS pins.
Scan control is supplied with user specific patterns which
makes the ’PSC100F protocol-independent. Overflow and
underflow conditions are prevented by stopping the test
clock.A32-bit counter is used to program the number of TCK
cycles required to complete a scan operation within the
boundary scan chain or to complete a ’PSC100F Built-In Self
Test (BIST) operation. SCANPSC100F device drivers and
1149.1 embedded test application code are available with
National’s SCANEase software tools.
Features
n
Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
n
Supported by National’s SCAN Ease (Embedded
Application Software Enabler) Software
n
Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n
Directly supports up to two 1149.1 scan chains
n
16-bit Serial Signature Compaction (SSC) at the Test
Data In (TDI) port
n
Automatically produces pseudo-random patterns at the
Test Data Out (TDO) port
n
Fabricated on FACT
1.5 μm CMOS process
n
Supports 1149.1 test clock (TCK) frequencies up to
25 MHz
n
TTL-compatible inputs; full-swing CMOS outputs with
24 mA source/sink capability
n
Standard Microcircuit Drawing (SMD) 5962-9475001
Connection Diagrams
FACT
is a trademark of Fairchild Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
28-Pin DIP and Flatpak
DS100325-1
Pin Assignment for LCC
DS100325-18
September 1998
S
1999 National Semiconductor Corporation
DS100325
www.national.com
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相關代理商/技術參數 |
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| SCANPSC100FLMQB | 制造商:Texas Instruments 功能描述: |
| SCANPSC100FSC | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC100FSCX | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC110 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110_ZFC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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