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參數資料
| 型號： | SI5017-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 1/26頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 28MLP |
| 標準包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數據恢復（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH，ATM 應用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-MLP-EP（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1279 |
Rev. 1.5 6/08
Copyright 2008 by Silicon Laboratories
Si5023
Si5017
OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
Features
High-speed clock and data recovery device with integrated limiting amplifier:
Applications
Description
The Si5017 is a fully-integrated, high-performance limiting amplifier (LA)
and clock and data recovery (CDR) IC for high-speed serial
communication systems. It derives timing information and data from a
serial input at OC-48 and STM-16 rates. Support for 2.7 Gbps data
streams is also provided for OC-48/STM-16 applications that employ
forward error correction (FEC). Use of an external reference clock is
optional. Silicon Laboratories DSPLL technology eliminates sensitive
noise entry points, thus making the PLL less susceptible to board-level
interaction and helping to ensure optimal jitter performance.
The Si5017 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
Supports OC-48/STM-16 and
2.7 Gbps FEC
DSPLL technology
Jitter generation 3.0 mUIrms (typ)
Small footprint: 5 x 5 mm
Loss-of-signal level alarm
Data slicing level control
10 mVPP differential sensitivity
3.3 V supply
Reference and reference-less
operation supported
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Limiting
Amp
DSPLL
Lock
Detection
Retim er
Reset/
Calibration
Bias Gen.
BUF
CLKOUT+
CLKOUT–
DIN+
DIN–
REFCLK+
REFCLK–
(Optional)
LOS
LOL
REXT
RESET/CAL
SLICE_LVL
DSQLCH
CLK_DSBL
LTR
Signal
Detect
LOS_LVL
BER_LVL
BER
Monitor
DOUT+
DOUT–
2
BER_ALM
Ordering Information:
See page 22.
Pin Assignments
Si5017
GND
Pad
1
2
3
4
5
VDD
LOS_LVL
REFCLK+
VDD
SLICE_LVL
6
7
LOL
REFCLK–
21
20
19
18
17
REXT
RESET/CAL
DOUT+
VDD
16
15 TDI
DOUT–
8
9 10 11 12
LO
S
DS
Q
LC
H
DIN+
LTR
VD
D
13 14
VD
D
DIN–
28 27 26 25 24
BE
R
_ALM
B
E
R_
LV
L
C
L
KD
SB
L
NC
VDD
23 22
CL
K
O
UT
–
CL
K
O
UT
+
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SI5017-D-GMR | 功能描述:時鐘發生器及支持產品 OC48/STM16 CDR FEC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5017-EVB | 功能描述:時鐘和定時器開發工具 OC48 STM16 SNT/SDH 2.7Gbps w/ limit amp RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5017-X-GM | 制造商:SILABS 制造商全稱:SILABS 功能描述:OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| SI5018 | 制造商:SILABS 制造商全稱:SILABS 功能描述:SiPHY⑩ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC |
| SI-50182 | 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:SI-50182 |
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