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參數資料
型號: SIC417CD-T1-E3
廠商: Vishay Siliconix
文件頁數: 9/19頁
文件大小: 922K
描述: IC REG DL BCK/LINEAR SYNC 32MLPQ
標準包裝: 1
系列: microBUCK®
拓撲: 降壓(降壓)同步(1),線性(LDO)(1)
功能: 任何功能
輸出數: 2
頻率 - 開關: 200kHz ~ 1MHz
電壓/電流 - 輸出 1: 0.5 V ~ 5.5 V,10A
電壓/電流 - 輸出 2: 0.75 V ~ 5.25 V,150mA
帶 LED 驅動器:
帶監控器:
帶序列發生器:
電源電壓: 3 V ~ 28 V
工作溫度: -25°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 32-PowerWFQFN
供應商設備封裝: PowerPAK? MLP55-32
包裝: 標準包裝
其它名稱: SIC417CD-T1-E3DKR
Vishay Siliconix
SiC417
Document Number: 69062
S10-1367-Rev. D, 14-Jun-10
www.vishay.com
9
Ultrasonic Power-Save Operation
The SiC417 provides ultra-sonic power-save operation at
light loads, with the minimum operating frequency fixed at
25 kHz. This is accomplished using an internal timer that
monitors the time between consecutive high-side gate
pulses.
If the time exceeds 40 祍, DL drives high to turn the low-side
MOSFET on. This draws current from V
OUT
 through the
inductor, forcing both V
OUT
 and V
FB
 to fall. When V
FB
 drops
to the 500 mV threshold, the next DH on-time is triggered.
After the on-time is completed the high-side MOSFET is
turned off and the low-side MOSFET turns on, the low-side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low-side MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40 祍, the frequency will not fall below ~ 25 kHz.
Figure 5 shows ultra-sonic power-save operation.
Benefits of Ultrasonic Power-Save
Having a fixed minimum frequency in power-save has some
significant advantages as below:
" The minimum frequency of 25 kHz is outside the audible
range of human ear. This makes the operation of the
SiC417 very quiet.
" The output voltage ripple seen in power-save mode is
significant lower than conventional power-save, which
improves efficiency at light loads.
" Lower ripple in power-save also makes the power
component selection easier.
Figure 6 shows the behavior under power-save and
continuous conduction mode at light loads.
Smart Power-Save Protection
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with power-
savepower-save enabled, this can force V
OUT
 to slowly rise
and reach the over-voltage threshold, resulting in a hard
shutdown. Smart power-save prevents this condition.
When the FB voltage exceeds 10 % above nominal (exceeds
550 mV), the device immediately disables power-save, and
DL drives high to turn on the low-side MOSFET. This draws
current from V
OUT
 through the inductor and causes V
OUT
 to
fall. When V
FB
 drops back to the 500 mV trip point, a normal
t
ON
 switching cycle begins.
This method prevents a hard OVP shutdown and also cycles
energy from V
OUT
 back to V
IN
. It also minimizes operating
power by avoiding forced conduction mode operation.
Figure 7 shows typical waveforms for the smart power-save
feature.
Figure 4 - Forced Continuous Mode Operation
Figure 5 - Ultrasonic power-save Operation
FB ripple
voltage (VFB)
Inductor
current
DC load current
FB threshold
(500 mV)
DH
DL
On-time
(t
ON
)
DH on-time is triggered when
V
FB
 reaches the FB threshold
DL drives high when on-time is completed.
DL remains high until V
FB
 falls to the FB threshold.
FB ripple
voltage (VFB)
Inductor
current
(0A)
FB threshold
(500 mV)
DH
DL
On-time
(t
ON
)
DH on-time is triggered when
V
FB
 reaches the FB threshold
After the 40 祍 time-out, DL drives high if V
FB
 
has not reached the FB threshold.
minimum f
SW
 
~
 25 kHz
Figure 6 - Ultrasonic Power-Save Operation Mode
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