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參數資料
| 型號： | SMJ320C40TBBM40/10 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, UUC325 |
| 封裝： | DIE-325 |
| 文件頁數： | 1/61頁 |
| 文件大小： | 1103K |
| 代理商： | SMJ320C40TBBM40/10 |
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SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017E – OCTOBER 1993 – REVISED SEPTEMBER 1999
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
D SMJ: QML Processing to MIL–PRF–38535
D SM: Standard Processing
D TMP: Commercial Level Processing TAB
D Operating Temperature Ranges:
– Military (M) – 55
°C to 125°C
– Special (S) – 55
°C to 100°C
– Commercial (C) – 25
°C to 85°C
– Commercial (L) 0
°C to 70°C
D Highest Performance Floating-Point Digital
Signal Processor (DSP)
– ’C40-60:
33-ns Instruction Cycle Time:
60 MFLOPS, 30 MIPS, 330 MOPS,
384 MBps
– ’C40-50:
40-ns Instruction Cycle Time:
50 MFLOPS, 25 MIPS, 275 MOPS,
320 MBps
– ’C40-40:
50-ns Instruction Cycle Time:
40 MFLOPS, 20 MIPS, 220 MOPS,
256 MBps
D Six Communications Ports
D 6-Channel Direct Memory Access (DMA)
Coprocessor
D Single-Cycle Conversion to and From
IEEE-745 Floating-Point Format
D Single Cycle 1/x, 1/
D Source-Code Compatible With SMJ320C30
D Validated Ada Compiler
D Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
D 12 40-Bit Registers, 8 Auxiliary Registers,
14 Control Registers, and 2 Timers
D IEEE Standard 1149.1 Test-Access Port
(JTAG)
D Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
– High Port-Data Rate of 100 MBytes/s
(Each Bus)
– 16G-Byte Continuous
Program/Data/Peripheral Address Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-, Data-, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
D Packaging:
– 325-Pin Ceramic Grid Array (GF Suffix)
– 352-Lead Ceramic Quad Flatpack
(HFH Suffix)
– 324-Pad JEDEC-Standard TAB Frame
D Fabricated Using 0.72-m Enhanced
Performance Implanted CMOS (EPIC
)
Technology by Texas Instruments (TI
)
D Separate Internal Program, Data, and DMA
Coprocessor Buses for Support of Massive
Concurrent Input/Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance
D On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache
– 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Bootloader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories Over Any One of the
Communications Ports
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1999, Texas Instruments Incorporated
x
IEEE Standard 1149.1- 1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
EPIC and TI are trademarks of Texas Instruments Incorporated.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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