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參數資料
| 型號： | SN54ALVTH16821WD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, CDFP56 |
| 封裝： | 0.380 INCH, CERAMIC, FP-56 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 196K |
| 代理商： | SN54ALVTH16821WD |
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V VCC)
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D High-Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V VCC)
D Power Off Disables Outputs, Permitting
Live Insertion
D High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
D Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D Auto3-State Eliminates Bus Current
Loading When Output Exceeds VCC + 0.5 V
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
D Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V
VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered
D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the
D inputs.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
SN54ALVTH16821 . . . WD PACKAGE
SN74ALVTH16821 ... DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus is a trademark of Texas Instruments Incorporated.
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