- 您現在的位置：買賣IC網 > PDF目錄98085 > SN54ALVTH32374KR (TEXAS INSTRUMENTS INC) ALVT SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96 PDF資料下載
參數資料
| 型號： | SN54ALVTH32374KR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | ALVT SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96 |
| 封裝： | PLASTIC, MO-205CC, FBGA-96 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 226K |
| 代理商： | SN54ALVTH32374KR |
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 – SEPTEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V VCC)
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D High Drive (–24/24 mA at 2.5-V VCC and
–32/64 mA at 3.3-V VCC)
D Ioff and Power-Up 3-State Support Hot
Insertion
D Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
NOTE: For tape and reel order entry:
The GKER package is abbreviated to KR.
D Auto3-State Eliminates Bus Current
Loading When Output Exceeds VCC + 0.5 V
D Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D ESD Protection Exceeds JESD-22
– 2000-V Human-Body Model
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
(A114-A)
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D Packaged in Plastic Fine-Pitch Ball Grid
Array Package
description
The ’ALVTH32374 devices are 32-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V
or 3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive
transition of the clock (CLK), the Q outputs of the flip-flops take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH32374 is characterized for operation over the full military temperature range of –55
°C to
125
°C. The SN74ALVTH32374 is characterized for operation from –40°C to 85°C.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
相關PDF資料 |
PDF描述 |
|---|---|
| SN54AS174FK | AS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20 |
| SN54AS175BJ | AS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| SN74AS175BDRG4 | AS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| SN54AS181BFK | AS SERIES, 4-BIT ARITHMETIC LOGIC UNIT, CQCC28 |
| SNJ54AS181BJW | AS SERIES, 4-BIT ARITHMETIC LOGIC UNIT, CDIP24 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN54AS00J | 制造商:Texas Instruments 功能描述:QUAD 2-INPUT NAND GATE - Rail/Tube |
| SN54AS04J | 制造商:Texas Instruments 功能描述:HEX INVERTER - Rail/Tube |
| SN54AS08J | 制造商:Texas Instruments 功能描述:AND Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Texas Instruments 功能描述:AND GATE 4-ELEM 2-IN BIPOLAR 14CDIP - Rail/Tube |
| SN54AS08W | 制造商:Texas Instruments 功能描述: |
| SN54AS1004AJ | 制造商:Texas Instruments 功能描述:Driver 6-CH Inverting Bipolar 14-Pin CDIP Tube |
發布緊急采購，3分鐘左右您將得到回復。