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參數資料
| 型號： | SN54LS74J |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Serial-Input/Parallel-Output Shift Register; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55 |
| 中文描述： | 雙路D類上升沿觸發器 |
| 文件頁數： | 1/3頁 |
| 文件大小： | 73K |
| 代理商： | SN54LS74J |
5-72
FAST AND LS TTL DATA
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.
LOGIC DIAGRAM
(Each Flip-Flop)
SET (SD)
4 (10)
CLEAR (CD)
1 (13)
CLOCK
3 (11)
D
2 (12)
Q
5 (9)
Q
6 (8)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
SD
L
H
L
H
H
SD
H
L
L
H
H
D
Q
Q
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)
X
X
X
h
l
H
L
H
H
L
L
H
H
L
H
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then
we cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
i, h (q) =
prior to the HIGH to LOW clock transition.
SN54/74LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
VCC = PIN 14
GND = PIN 7
2
3
5
D
Q
CP
Q
CD
1
4
6
12
11
9
D
Q
CP
Q
CD
13
10
8
SD
SD
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