- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄374864 > SN74ALVCH16270DGG (Texas Instruments, Inc.) 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS PDF資料下載
參數(shù)資料
| 型號(hào)： | SN74ALVCH16270DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS |
| 中文描述： | 12位到24位注冊(cè)巴士換熱具有三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 138K |
| 代理商： | SN74ALVCH16270DGG |
SN74ALVCH16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES028F – JULY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16270 is used in applications in
which data must be transferred from a narrow
high-speed bus to a wide lower-frequency bus.
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input when the appropriate
CLKEN inputs are low. The select (SEL) line
selects 1B or 2B data for the A outputs. For data
transfer in the A-to-B direction, a two-stage
pipeline is provided in the A-to-1B path, with a
single storage register in the A-to-2B path.
Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a
24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control
terminals are registered to synchronize the bus-direction changes with CLK.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible and OE should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16270 is characterized for operation from –40
°
C to 85
°
C.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEA
CLKEN1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
CLKEN2B
SEL
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ALVCH16271DGG | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 150pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: 100% Tin (Sn); Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate |
| SN74ALVCH16271DL | 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS |
| SN74ALVCH162721DGG | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 150pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: 100% Tin (Sn); Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate |
| SN74ALVCH162820DGG | 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS |
| SN74ALVCH162827DGV | 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ALVCH16270DGGR | 功能描述:通用總線函數(shù) 12-24bit Reg Bus RoHS:否 制造商:Texas Instruments 邏輯類(lèi)型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVCH16270DL | 功能描述:通用總線函數(shù) 12-24bit Reg Bus RoHS:否 制造商:Texas Instruments 邏輯類(lèi)型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVCH16270DLR | 功能描述:通用總線函數(shù) 12-24bit Reg Bus RoHS:否 制造商:Texas Instruments 邏輯類(lèi)型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVCH16271DGGR | 功能描述:通用總線函數(shù) 12-24bit Reg Bus RoHS:否 制造商:Texas Instruments 邏輯類(lèi)型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVCH16271DL | 功能描述:通用總線函數(shù) 12-24bit Reg Bus RoHS:否 制造商:Texas Instruments 邏輯類(lèi)型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。