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參數資料
| 型號： | SN74GTL16612ADLR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | GTL/TVC SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, SSOP-56 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 234K |
| 代理商： | SN74GTL16612ADLR |
www.ti.com
FEATURES
DESCRIPTION
Drvr
VTT
Conn.
0.25”
0.875”
0.625”
1”
Slot 1
Slot 2
VTT
0.625”
1”
Slot 16
Slot 8
0.25”
R
TT
Conn.
Rcvr
R
TT
V
olts
V
t Time ns
10
30
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0
20
TI GTL16612A
Fairchild GTLP16612
TI GTL16612
SN54GTL16612A, SN74GTL16612A
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED JULY 2005
Bus Hold on A-Port Inputs Eliminates the
Need for External Pullup/Pulldown Resistors
Members of the Texas Instruments Widebus
Family
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
Universal Bus Transceiver (UBT) Combines
D-Type Latches and D-Type Flip-Flops for
ESD Protection Exceeds JESD 22
Operation in Transparent, Latched, Clocked,
– 2000-V Human-Body Model (A114-A)
or Clock-Enabled Modes
– 200-V Machine Model (A115-A)
Translate Between GTL/GTL+ Signal Levels
– 1000-V Charged-Device Model (C101)
and LVTTL Logic Levels
Latch-Up Performance Exceeds 100 mA Per
Support Mixed-Mode (3.3-V and 5-V) Signal
JESD 78, Class II
Operation on A-Port and Control Inputs
Package Options Include Plastic Shrink
B-Port Transition Time Optimized for
Small-Outline (DL), Thin Shrink Small-Outline
Distributed Backplane Loads
(DGG), and Ceramic Flat (WD) Packages
Ioff Supports Partial-Power-Down Mode
xxx
Operation
The 'GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes of
data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels and
backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL)
backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
output edge control (OEC). Improved GTL+ OEC circuits minimize bus settling time and have been designed
and tested using several backplane models.
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is a
16-slot, 14-inch board with loaded impedance of 33
. V
TT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 .
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot-1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data, and the system clock frequency is
limited by the backplane flight time to about 80-90 MHz. This frequency can be increased even more (30% to
40%) if the clock is generated and transmitted together with the data from the driver card (source synchronous).
Figure 1. Test Backplane Model With Output Waveform Results
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1999–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74GTL16612DGGR | 功能描述:轉換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DL | 功能描述:轉換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DLG4 | 功能描述:轉換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DLR | 功能描述:轉換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DLRG4 | 功能描述:轉換 - 電壓電平 3-8-Line Decoder Demltplxr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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