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參數資料
| 型號： | SN74GTLP1394DR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | GTLP SERIES, 2-BIT TRANSCEIVER, CONFIGURABLE OUTPUT, PDSO16 |
| 封裝： | GREEN, PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數： | 1/24頁 |
| 文件大小： | 552K |
| 代理商： | SN74GTLP1394DR |
www.ti.com
FEATURES
D, DGV, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
16
8
9
2
3
4
5
6
7
15
14
13
12
11
10
GND
B1
GND
B2
GND
VREF
Y1
Y2
VCC
A1
A2
OEAB
OEBY
T/C
BIAS
V
ERC
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OEBY
Y1
Y2
VCC
A1
A2
OEAB
ERC
BIAS VCC
GND
B1
GND
B2
GND
VREF
T/C
DESCRIPTION/ORDERING INFORMATION
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2005
Data-Transfer Rate and Signal Integrity in
Distributed Loads
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
OEC Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Polarity Control Selects True or
Complementary Outputs
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
ESD Protection Exceeds JESD 22
LVTTL Interfaces Are 5-V Tolerant
– 2000-V Human-Body Model (A114-A)
High-Drive GTLP Outputs (100 mA)
– 200-V Machine Model (A115-A)
LVTTL Outputs (–24 mA/24 mA)
– 1000-V Charged-Device Model (C101)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
QFN – RGY
Tape and reel
SN74GTLP1394RGYR
GP1394
Tube
SN74GTLP1394D
SOIC – D
GTLP1394
–40°C to 85°C
Tape and reel
SN74GTLP1394DR
TSSOP – PW
Tape and reel
SN74GTLP1394PWR
GP394
TVSOP – DGV
Tape and reel
SN74GTLP1394DGVR
GP394
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1999–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74GTLP1394DRE4 | 功能描述:轉換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394DRG4 | 功能描述:轉換 - 電壓電平 2B LVTTL to GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PW | 功能描述:轉換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PWE4 | 功能描述:轉換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PWG4 | 功能描述:轉換 - 電壓電平 2B LVTTL to GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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