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參數資料
| 型號： | SN74LS75N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 500mA, 15V,±4% Tolerance, Negative Voltage Regulator, Ta = -40°C to +125°C; Package: DPAK 4 LEAD Single Gauge Surface Mount; No of Pins: 4; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 98K |
| 代理商： | SN74LS75N |
NOTES:
tn = bit time before enable
negative-going transition
tn+1 = bit time after enable
negative-going transition
5-75
FAST AND LS TTL DATA
4-BIT D LATCH
The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-
porary storage for binary information between processing units and input/out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54/74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54/74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
CONNECTION DIAGRAMS DIP
(TOP VIEW)
SN54/74LS75
14
13
12
11
10
9
1
2
3
4
5
6
D3
8
7
SN54/74LS77
Q0
Q0
Q1
Q1
E0–1
GND
Q2
Q2
Q3
D0
D1
E2–3
VCC
D2
D3
Q3
Q0
Q1
E0–1
GND
NC
Q2
Q3
D0
D1
E2–3
VCC
D2
NC
PIN NAMES
LOADING
(Note a)
HIGH
LOW
D1–D4
E0–1
E2–3
Q1–Q4
Q1–Q4
NOTES:
a) 1 Unit Load (U.L.) = 40
μ
A HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
TRUTH TABLE
(Each latch)
tn
D
H
L
tn+1
Q
H
L
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
14
1
D SUFFIX
SOIC
CASE 751A-02
相關PDF資料 |
PDF描述 |
|---|---|
| SN74LS75 | 4-BIT D LATCH LOW POWER SCHOTTKY |
| SN74LS77 | 4-BIT D LATCH LOW POWER SCHOTTKY |
| SN74LS798DW | TRI-STATE OCTAL BUFFERS |
| SN54LS795 | 8-Bit Serial or Parallel-Input/Serial Output Shift Register; Package: PDIP-16; No of Pins: 16; Container: Rail; Qty per Container: 500 |
| SN54LS795J | Hex D-Type Flip-Flop with Clock; Package: SOIC 16 LEAD; No of Pins: 16; Container: Rail; Qty per Container: 48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74LS75N | 制造商:Texas Instruments 功能描述:IC 74LS 74LS75 DIP16 5.25V 制造商:Texas Instruments 功能描述:IC, 74LS, 74LS75, DIP16, 5.25V 制造商:Texas Instruments 功能描述:IC, 74LS, 74LS75, DIP16, 5.25V; Logic Type:Bistable Latch; Logic Case Style:DIP; No. of Pins:16; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Operating Temperature Min:0C; Operating Temperature Max:70C; SVHC:No SVHC ;RoHS Compliant: Yes |
| SN74LS75N | 制造商:Texas Instruments 功能描述:IC 74LS 74LS75 DIP16 5.25V |
| SN74LS75NE4 | 功能描述:閉鎖 Quad bistable latch RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LS75NSR | 功能描述:閉鎖 Quad bistable latch RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LS75NSRE4 | 功能描述:閉鎖 Quad bistable latch RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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