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參數(shù)資料
| 型號： | SSI1N50B |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | 520V N-Channel MOSFET |
| 中文描述： | 1.5 A, 520 V, 5.3 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | I2PAK-3 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 600K |
| 代理商： | SSI1N50B |
2002 Fairchild Semiconductor Corporation
Rev. C, May 2002
S
SSW1N50B / SSI1N50B
520V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies,
power factor correction and electronic lamp ballasts based
on half bridge.
Features
1.5A, 520V, R
DS(on)
= 5.3
@V
GS
= 10 V
Low gate charge ( typical 8.3 nC)
Low Crss ( typical 5.5 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Absolute Maximum Ratings
T
C
= 25°C unless otherwise noted
Thermal Characteristics
* When mounted on the minimum pad size recommended (PCB Mount)
Symbol
V
DSS
I
D
Parameter
SSW1N50B / SSI1N50B
520
1.5
0.97
5.0
±
30
100
1.5
3.6
5.5
3.13
36
0.29
-55 to +150
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
Drain-Source Voltage
Drain Current
- Continuous (T
C
= 25°C)
- Continuous (T
C
= 100°C)
- Pulsed
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
Drain Current
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
A
= 25°C) *
Power Dissipation (T
C
= 25°C)
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
- Derate above 25°C
T
J
, T
stg
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8
"
from case for 5 seconds
T
L
300
°C
Symbol
R
θ
JC
R
θ
JA
R
θ
JA
Parameter
Typ
--
--
--
Max
3.44
40
62.5
Units
°C
/
W
°C
/
W
°C
/
W
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
●
●
●
●
●
▲
!
!
S
!
!
!
D
G
D
2
-PAK
SSW Serie
s
I
2
-PAK
SSI Series
G
S
D
G
S
D
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