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參數資料
| 型號： | SSM6N7002FU_07 |
| 廠商： | Toshiba Corporation |
| 英文描述： | High Speed Switching Applications |
| 中文描述： | 高速開關應用 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 174K |
| 代理商： | SSM6N7002FU_07 |
SSM6N7002FU
2007-11-01
1
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type
SSM6N7002FU
High Speed Switching Applications
Analog Switch Applications
Small package
Low ON resistance
: R
on
=
3.3
Ω
(max) (@V
GS
=
4.5 V)
: R
on
=
3.2
Ω
(max) (@V
GS
=
5 V)
: R
on
=
3.0
Ω
(max) (@V
GS
=
10 V)
Absolute Maximum Ratings
(Ta = 25°C)
(Q1, Q2 Common)
Characteristics
Symbol
Rating
Unit
Drain-Source voltage
Gate-Source voltage
V
DS
V
GSS
I
D
I
DP
P
D
(Note 1)
T
ch
T
stg
60
±
20
200
800
300
150
55~150
V
V
DC
Pulse
Drain current
mA
Drain power dissipation (Ta
=
25°C)
Channel temperature
Storage temperature range
Note:
Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual
reliability data (i.e. reliability test report and estimated failure
rate, etc).
Note 1: Total rating, mounted on FR4 board
(25.4 mm
×
25.4 mm
×
1.6 t, Cu Pad: 0.32mm
2
×
6)
mW
°C
°C
Marking
Equivalent Circuit
(top view)
6
5
Handling Precaution
When handling individual devices (which are not yet mounting on a circuit board), be sure that the environment is
protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects
that come into direct contact with devices should be made of anti-static materials.
Unit: mm
JEDEC
―
JEITA
―
TOSHIBA
2-2J1C
NC
6
5
4
1
2
3
Q1
Q2
4
1
2
3
0.4 mm
0
1.SOURCE1
2.GATE1
3.DRAIN2
4.SOURCE2
5.GATE2
6.DRAIN1
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