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參數(shù)資料
型號: SSTV16857MTDX
元件分類: 通用總線功能
英文描述: Memory Driver
中文描述: 記憶體驅(qū)動
文件頁數(shù): 1/6頁
文件大小: 76K
代理商: SSTV16857MTDX
2001 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com
September 2000
Revised February 2001
S
SSTV16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin DDR-I memory modules. The device has
a differential input clock, SSTL-2 compatible data inputs
and a LVCMOS compatible RESET input. The device has
been designed for compliance with the JEDEC DDR mod-
ule and register specifications.
The device is fabricated on an advanced submicron CMOS
process and is designed to operate at power supplies of
less than 3.6V’s.
Features
I
Compliant with DDR-I registered module specifications
I
Operates at 2.5V
±
0.2V V
DD
I
SSTL-2 compatible input and output structure
I
Differential SSTL-2 compatible clock inputs
I
Low power mode when device is reset
I
Industry standard 48 pin TSSOP package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
X
to the ordering code.
Connection Diagram
Pin Descriptions
Truth Table
L
=
Logic LOW
H
=
Logic HIGH
X
=
Don
t Care, but not floating unless noted
=
LOW-to-HIGH Clock Transition
=
HIGH-to-LOW Clock Transition
Order Number
SSTV16857MTD
Package Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Name
Q
1
-Q
14
D
1
-D
14
RESET
CK
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
V
REF
V
DDQ
V
DD
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
RESET
L
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
L
H
CK
X or
Floating
H
L
Q
n
L
H
H
H
H
L
H
Q
n
Q
n
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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