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參數(shù)資料
型號(hào): STP1081ABGA-150
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256
封裝: PLASTIC, BGA-256
文件頁(yè)數(shù): 1/32頁(yè)
文件大?。?/td> 478K
代理商: STP1081ABGA-150
DATA SHEET
1
STP1081
UltraSPARC
-II Data Buffer (UDB-II)
Companion Device for 250/300 MHz UltraSPARC-II Systems
DESCRIPTION
The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro-
processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the
most-signicant data bits) and UDB_L (for the least-signicant data bits). The UDB-II moves data between the
E-Cache bus and the UPA data bus (see Figure 1), enabling the system to send data to and receive data from
the faster CPU transparently. The E-Cache bus has 128 data bits and 16 parity bits, for a total width of 144 bits.
The data bus is also 144 bits wide, including 128 data bits and 16 error-correction code (ECC) bits. Noncache-
able loads and stores use the E-Cache bus for moving data to the data buffer located in UDB_H and UDB_L.
The UDB-II (model STP1081ABGA) is built with leading-edge CMOS ASIC technology featuring 0.5-micron
geometries, and a three-layer metal process. It operates at 2.6 V and 3.3 V.
Features
Benets
Isolates the processor from the system bus
High performance: ease of design
Interface to the UPA
Fully synchronous design
Operates at system frequency
Operates at half the processor frequency
Provides data buffering
Supports parity on the CPU side and ECC on the system
side
Stores interrupt vectors. Interrupt registers visible to
software
Enables secondary cache transfers and system memory
transfers by isolation
IEEE standard 1149.1 (JTAG) boundary scan test
Ease of manufacturing test
256 PBGA package
Small footprint and cost effective packaging
July 1997
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