參數資料
| 型號： | SY100S839VZI TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/6頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 3.3V/5V 20-SOIC |
| 標準包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 時鐘發生器 |
| PLL： | 無 |
| 輸入： | ECL，LVECL，LVPECL，PECL |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC（寬型） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100S839VZITR SY100S839VZITR-ND |
1
Precision Edge
SY100S839V
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
The SY100S839V is a low skew
÷2/4, ÷4/5/6 clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or, if
positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the VBB output, a sinusoidal
source can be AC-coupled into the device. If a single-
ended input is to be used, the VBB output should be
connected to the /CLK input and bypassed to ground via
a 0.01
F capacitor. The VBB output is designed to act as
the switching reference for the input of the S839V under
single-ended input conditions. As a result, this pin can
only source/sink up to 0.5mA of current.
The common enable (/EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input must be
asserted to ensure synchronization. For systems which
only use one S839V, the MR pin need not be exercised
as the internal divider designs ensures synchronization
between the
÷2/4, and the ÷4/5/6 outputs of a single
device.
s 3.3V and 5V power supply option
s 50ps output-to-output skew
s 50% duty cycle outputs
s Synchronous enable/disable
s Master Reset for synchronization
s Internal 75K
input pull-down resistors
s Available in 20-pin SOIC package
DESCRIPTION
FEATURES
Rev.: B
Amendment: /0
Issue Date:
March 2006
÷2/4, ÷4/5/6 CLOCK
GENERATION CHIP
Precision Edge
SY100S839V
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge
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