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參數(shù)資料
| 型號(hào)： | SY100S891JZ TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX 5BIT REGISTERED 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 100S |
| 邏輯類型： | 寄存收發(fā)器，非反相 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 5 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100S891JZTR SY100S891JZTR-ND |
1
SY100S891
Micrel, Inc.
M9999-032406
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
BUSEN0–4
Bus Enable Inputs
D0 – D4
Data Inputs
CLK1
Bus Driver Clock Input
CLK2
Receive Register Clock
MR
Master Reset
Q0 – Q4
Bus Receive Outputs
BUS0–4
Bus Outputs
DESCRIPTION
FEATURES
s 25
cut-off bus outputs
s 50
receiver outputs
s Transmit and receive registers with separate clocks
s 1500ps max. delay from CLK1 to Bus Outputs (BUS)
s 1500ps max. delay from CLK2 to Receiver Outputs (Q)
s Individual bus enable pins
s Internal 75K
input pull-down resistors
s Voltage and temperature compensation for improved
noise immunity
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Available in 28-pin PLCC package
The SY100S891 is a 5-bit registered transceiver
containing five bus transceivers with both transmit and
receive registers. The bus outputs (BUS0 – BUS4) are
specified for driving a 25 ohm bus and the receive outputs
(Q0 – Q4) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN0 – BUSEN4) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a clock (CLK1) which is common to all five bus driver
registers; and a separate clock (CLK2) which is common
to all five receive registers. Data at the D inputs is clocked
to the Bus register by a positive transition of CLK1 and
data on the bus is clocked into the Receiver register by
a positive transition of CLK2. A high on the Master Reset
clears all registers.
5-BIT REGISTERED
TRANSCEIVER
PIN NAMES
SY100S891
Rev.: F
Amendment: /0
Issue Date:
March 2006
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