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參數資料
| 型號： | T35L6432B-10Q |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁數： | 1/16頁 |
| 文件大小： | 162K |
| 代理商： | T35L6432B-10Q |
TE
CH
tm
SYNCHRONOUS
BURST SRAM
T35L6432B
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A
64K x 32 SRAM
Flow-Through Burst Mode
FEATURES
Fast Access times: 9 / 10 / 11 / 12 ns
Single 3.3V (+0.3V/-0.165V) power supply
Common data inputs and data outputs
Individual BYTE WRITE ENABLE and
GLOBAL WRITE control
Three chip enables for depth expansion and
address pipelining
Clock-controlled and registered address, data
I/Os and control signals
Internally self-timed WRITE CYCLE
Burst control pins ( interleaved or linear burst
sequence)
High 30pF output drive capability at rated access
time
SNOOZE MODE for reduced power standby
Burst Sequence :
- Interleaved (MODE=NC or VCC)
- Linear (MODE=GND)
OPTIONS
MARKING
-9
Access
time
through
2-1-1-1
time
PACKAGE package code
100-pin QFP Q
100-pin TQFP T
Part Number Examples
-10
-11
-12
9ns
10ns
11ns
12ns
Flow-
Cycle
10.5ns
15ns
15ns
15ns
PART NO.
T35L6432B-10Q
T35L6432B-12T
speed
10ns
12ns
Package
QFP
TQFP
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs high-speed, low power
CMOS design using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell
consists of four transistors and two high valued resistors.
The T35L6432B SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (
CE
), depth-
expansion chip enables (
CE2
and CE2), burst control
inputs (
ADSC
,
ADSP
, and
ADV
), write enables
(
BW1
,
BW2
,
BW3
,
BW4
, and
BWE
), and
global write (
GW
).
Asynchronous inputs include the output enable
(
OE
), Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by
OE
, are
also asynchronous.
Addresses and chip enables are registered with
either address status processor (
ADSP
) or address
status controller (
ADSC
) input pins. Subsequent burst
addresses can be internally generated as controlled by
the burst advance pin (
ADV
).
Address and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles
can be one to four bytes wide as controlled by the write
control inputs. Individual byte write allows individual
byte to be written.
BW1
controls DQ1-DQ8.
BW2
controls DQ9-DQ16.
BW3
controls DQ17-
DQ 24.
BW4
controls DQ25-DQ32.
BW1
,
BW2
,
BW3
, and
BW4
can be active only with
BWE
being LOW.
GW
being LOW causes all
bytes to be written. WRITE pass-through capability
allows written data available at the output for the
immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
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PDF描述 |
|---|---|
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相關代理商/技術參數 |
參數描述 |
|---|---|
| T35L6432B-12T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6464A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
| T35L6464A-5L | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
| T35L6464A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
| T-35SP | 制造商:Triad Magnetics 功能描述: |
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