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參數(shù)資料
| 型號： | T35L6464A-5Q |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 64 SRAM |
| 中文描述： | 64K的× 64的SRAM |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 160K |
| 代理商： | T35L6464A-5Q |
TE
CH
tm
SYNCHRONOUS
BURST SRAM
FEATURES
Fast Access times: 5, 6, 7, and 8ns
Fast clock speed: 100, 83, 66, and 50 MHz
Provide high performance 3-1-1-1 access rate
Fast OE access times: 5 and 6ns
Single 3.3V +10% / -5V power supply
Common data inputs and data outputs
BYTE WRITE ENABLE and GLOBAL
WRITE control
Five chip enables for depth expansion and
address pipelining
Address, control, input, and output pipelined
registers
Internally self-timed WRITE cycle
WRITE pass-through capability
Burst control pins ( interleaved or linear burst
sequence)
High density, high speed packages
Low capacitive bus loading
High 30pF output drive capability at rated access
time
SNOOZE MODE for reduced power standby
Single cycle disable ( Pentium
TM
BSRAM
compatible )
OPTIONS
TIMING
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
Package
128-pin QFP
128-pin LQFP
Part Number Examples
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
64K x 64 SRAM
3.3V SUPPLY, FULLY REGISTERED AND OUTPUTS,
BURST COUNTER
MARKING
-5
-6
-7
-8
Q
L
PART NO.
T35L6464A-5Q
T35L6464A-5L
Pkg.
Q
BURST SEQUENCE
Interleaved
(MODE=NC or VCC)
Linear (MODE=GND)
L
PIN ASSIGNMENT
(Top View)
VSSQ
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
VCCQ
VSSQ
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
VCCQ
VSSQ
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
VCCQ
DQ8
DQ7
DQ9
DQ10
DQ11
VCCQ
VSSQ
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
VCCQ
VSSQ
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
VCCQ
1
2
11
12
10
9
8
7
6
5
4
3
18
19
17
16
15
14
13
28
29
27
26
25
24
23
22
21
20
30
31
32
33
34
35
36
37
38
39
49
48
47
46
45
44
43
42
41
40
57
56
55
54
53
52
51
50
58
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
92
91
90
89
88
87
86
85
84
83
102
101
100
99
98
97
96
95
94
93
123
124
116115114113112111110109
118
119
120
121
122
117
128127126125
C
V
C
O
B
B
B
B
C
V
V
C
C
C
B
B
G
B
V
V
V
A
A
A
A
V
A
A
A
A
A
A
A
V
A
A
Z
V
M
N
128-pin QFP
or
128-pin LQFP
63
62
61
60
59
64
V
A
A
A
N
V
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
108107106105104103
A
A
B
B
V
A
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS
design
using
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6464A SRAM integrates 65536 x 64
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, three active LOW
chip enable (CE ,CE2 and CE3), two additional
chip enables (CE2 and CE3) , burst control inputs
advanced
triple-layer
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