- 您現在的位置：買賣IC網 > PDF目錄16771 > TAS5615PHD2EVM (Texas Instruments)EVAL MODULE FOR TAS5615PHD2 PDF資料下載
參數資料
| 型號： | TAS5615PHD2EVM |
| 廠商： | Texas Instruments |
| 文件頁數： | 16/36頁 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR TAS5615PHD2 |
| 標準包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
www.ti.com
SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010
output LC filter. The typical duration is < 15 ms/mF. While the PPSC detection is in progress, SD is kept low, and
the device does not react to changes applied to the RESET pin. If no shorts are present, the PPSC detection
passes, and SD is released. A device reset does not start a new PPSC detection. PPSC detection is enabled in
BTL and PBTL output configurations; the detection is not performed in SE mode. To make sure not to trip the
PPSC detection system, it is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options have individual overtemperature protection schemes.
PHD Package
The TAS5615 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5615 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5615 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach levels stated in the Electrical Characteristics
table. Although GVDD_X and VDD are independently monitored, a supply-voltage drop below the UVP threshold
on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low.
Asserting the reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced
high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To
ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on the reset input allows the device to execute the start-up sequence and starts
switching.
Apply only audio when the state of READY is high; that starts and stops the amplifier without having audible
artifacts in the output transducers. If an overcurrent protection event is introduced, the READY signal goes low;
hence, filtering is needed if the signal is intended for audio muting in non-microcontroller systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used to decrease either an
audio volume or an intelligent power supply controlling a low and a high rail.
The device inverts the audio signal from input to output.
Copyright 2009–2010, Texas Instruments Incorporated
23
Product Folder Link(s) :TAS5615
相關PDF資料 |
PDF描述 |
|---|---|
| H3AAH-2606M | IDC CABLE - HSC26H/AE26M/HSC26H |
| 562A054-3/86-0 | BOOT MOLDED |
| RYM10DTKS | CONN EDGECARD 20POS DIP .156 SLD |
| V24B48E150BG | CONVERTER MOD DC/DC 48V 150W |
| HBM08DRTF-S13 | CONN EDGECARD 16POS .156 EXTEND |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TAS5615PHDR | 功能描述:音頻放大器 Analog input 160W RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5616 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:160-W STEREO / 300-W MONO PurePatha?￠ HD DIGITAL-INPUT POWER STAGE |
| TAS5616DKD | 功能描述:音頻放大器 PWM inp 150W Stereo class D Amplifier RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5616DKD2EVM | 功能描述:音頻 IC 開發工具 TAS5616DKD2 Eval Mod RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TAS5616DKDR | 功能描述:音頻放大器 PWM inp 150W Stereo class D Amplifier RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
發布緊急采購，3分鐘左右您將得到回復。