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| 型號： | TC9402EJD |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 545K |
| 描述： | IC V-FREQ/FREQ-V CONV 14CDIP |
| 標準包裝： | 29 |
| 類型： | 電壓至頻率和頻率至電壓 |
| 頻率 - 最大： | 100kHz |
| 全量程： | ±100ppm/°C |
| 線性： | ±0.25% |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CERDIP |
| 包裝： | 管件 |
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TC9400/9401/9402
DS21483D-page 6
?2007 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 Bias Current (I
BIAS
)
An external resistor, connected to V
SS
, sets the bias
point for the TC9400. Specifications for the TC9400 are
based on R
BIAS
= 100k??0%, unless otherwise
noted.
Increasing the maximum frequency of the TC9400
beyond 100kHz is limited by the pulse width of the
pulse output (typically 3祍). Reducing R
BIAS
will
decrease the pulse width and increase the maximum
operating frequency, but linearity errors will also
increase. R
BIAS
can be reduced to 20k? which will
typically produce a maximum full scale frequency of
500kHz.
2.2 Zero Adjust
This pin is the non-inverting input of the operational
amplifier. The low frequency set point is determined by
adjusting the voltage at this pin.
2.3 Input Current (I
IN
)
The inverting input of the operational amplifier and the
summing junction when connected in the V/F mode. An
input current of 10 糀 is specified, but an over range
current up to 50 糀 can be used without detrimental
effect to the circuit operation. I
IN
connects the summing
junction of an operational amplifier. Voltage sources
cannot be attached directly, butmust be buffered by
external resistors.
2.4 Voltage Capacitor (V
REF
Out)
The charging current for C
REF
is supplied through this
pin. When the op amp output reaches the threshold
level, this pin is internally connected to the reference
voltage and a charge, equal to V
REF
x C
REF
, is removed
from the integrator capacitor. After about 3約ec, this pin
is internally connected to the summing junction of the
op amp to discharge C
REF
. Break-before-make switch-
ing ensures that the reference voltage is not directly
applied to the summing junction.
2.5 Voltage Reference (V
REF
)
A reference voltage from either a precision source, or
the V
SS
supply is applied to this pin. Accuracy of the
TC9400 is dependent on the voltage regulation and
temperature characteristics of the reference circuitry.
Since the TC9400 is a charge balancing V/F converter,
the reference current will be equal to the input current.
For this reason, the DC impedance of the reference
voltage source must be kept low enough to prevent
linearity errors. For linearity of 0.01%, a reference
impedance of 200?or less is recommended. A 0.1礔
bypass capacitor should be connected from V
REF
to
ground.
Pin No.
Symbol
Description
1
I
BIAS
This pin sets bias current in the TC9400. Connect to V
SS
through a 100k?resistor.
2
ZERO ADJ Low frequency adjustment input.
3
I
IN
Input current connection for the V/F converter.
4
V
SS
Negative power supply voltage connection, typically -5V.
5
V
REF
OUT Reference capacitor connection.
6
GND Analog ground.
7
V
REF
Voltage reference input, typically -5V.
8
PULSE FREQ
OUT
Frequency output. This open drain output will pulse LOW each time the Freq.
Threshold Detector limit is reached. The pulse rate is proportional to input voltage.
9
OUTPUT
COMMON
Source connection for the open drain output FETs.
10
FREQ/2 OUT This open drain output is a square wave at one-half the frequency of the pulse output
(Pin 8). Output transitions of this pin occur on the rising edge of Pin 8.
11
THRESHOLD
DETECTOR
Input to the Threshold Detector. This pin is the frequency input during F/V operation.
12
AMPLIFIER OUT Output of the integrator amplifier.
13
NC
No internal connection.
14
V
DD
Positive power supply connection, typically +5V.
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