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參數資料
| 型號： | TFP6422PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁數： | 43/65頁 |
| 文件大小： | 813K |
| 代理商： | TFP6422PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
48
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VFLTR_CTRL
Subaddress = 56
Default = 0x00
7
6
5
4
3
2
1
0
SC_LOAD
SCBYPS
DEFLKR
INTP
Vertical interpolation control for 5-tap interpolation filter
0(*)
Single-phase nearest neighbor
1
Adaptive 32-phase interpolation
DEFLKR
Vertical deflicker filter cut-off frequency control
000(*) Near all-pass
001
–6dB at 3/8 cycle per line
010
–6dB at 5/16 cycle per line
011
–6dB at 1/4 cycle per line
100
–6dB at 3/16 cycle per line
101–111 Reserved
SCBYPS
Scaler Bypass
0(*)
Scaler is enabled
1
Scaler is bypassed
SC_LOAD
Load bit for scaling related registers to perform overscan compensation
0(*)
No effects.
1
Enables the content of the I2C registers for overscan compensation to be loaded into the
internal hardware registers. A 0 to 1 transition at SC_LOAD bit will trigger the loading.
SC_LOAD affects the following register bits:
CKENCSE
CKOUTSE
PLL_X [27:0]
PLL_X_SF[1:0]
PLL_Y[27:0]
PLL_Y_SF[1:0]
LLEN[10:0]
LLEN_EN
FLENS[10:0]
VRATIOR[9:0]
VRATIOQ[4:0]
VRATIOR2[9:0]
VRATIOQ2[4:0]
HFLTR_CTRL
Subaddress = 57
Default = 0x00
7
6
5
4
3
2
1
0
CINTP
YINTP
Luminance interpolation filter control
0(*)
The luminance interpolation filter is enabled
1
The luminance interpolation filter is bypassed
CINTP
Chrominance interpolation filter control
00(*)
The chrominance interpolation filter is enabled
01
The first section of the chrominance interpolation filter is bypassed
10
The second section of the chrominance interpolation filter is bypassed
11
Both sections of the filter are bypassed
PRODUCT
PREVIEW
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