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參數資料
型號: THS10064IDAR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: GREEN, PLASTIC, TSSOP-32
文件頁數: 20/42頁
文件大小: 527K
代理商: THS10064IDAR
THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
www.ti.com
27
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can
be selected, is dependent on the number of input channels. Both, a differential or a single-ended input is considered
as one channel. The processor therefore always reads the data from the FIFO in the same order and is able to
distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1
BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
TRIGGER LEVEL
FOR 3 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 4 CHANNELS
(ADC values)
0
01
02
03
04
0
1
04
06
08
1
0
08
09
12
1
14
12
Reserved
TIMING AND SIGNAL DESCRIPTION OF THE THS10064
The reading from the THS10064 and writing to the THS10064 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W).
This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The
two chip select inputs can be used to interface easily to a processor.
Reading from the THS10064 takes place by an internal RDint signal, which is generated from the logical combination
of the external signals CS0, CS1 and RD (see Figure 37). This signal is then used to strobe the words out of the FIFO
and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RDint active
while the write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates
RDint again.
Writing to the THS10064 takes place by an internal WRint signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers
0 and 1. The last external signal (either CS0, CS1 or WR) to become valid makes WRint active while the read input
(RD) is inactive. The first of those external signals going to its inactive state then deactivates WRint again.
Read Enable
Write Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 37. Logical Combination of CS0, CS1, RD, and WR
相關PDF資料
PDF描述
THS10064IDAG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS1007CDA 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS1007CDAR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS1007CDAG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS1007IDA 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
相關代理商/技術參數
參數描述
THS1007 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
THS1007CDA 功能描述:模數轉換器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
THS1007CDAG4 功能描述:模數轉換器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
THS1007CDAR 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
THS1007IDA 功能描述:模數轉換器 - ADC 10 BIT QUAD ADC w/o RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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