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參數(shù)資料
| 型號(hào)： | THS1040CDW |
| 廠(chǎng)商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁(yè)數(shù)： | 17/36頁(yè) |
| 文件大小： | 751K |
| 代理商： | THS1040CDW |
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THS1040
SLAS290C OCTOBER 2001 REVISED OCTOBER 2004
24
www.ti.com
APPLICATION INFORMATION
driving the THS1040 analog inputs
driving the clock input
Obtaining good performance from the THS1040 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter
at the CLK input, any clock buffers external to the THS1040 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an appropriate supply
voltage to drive above and below this level.
driving the sample and hold inputs
driving the AIN+ and AIN pins
Figure 32 shows an equivalent circuit for the THS1040 AIN+ and AIN pins. The load presented to the system
at the AIN pins comprises the switched input sampling capacitor, CSample, and various stray capacitances, C1
and C2.
C1
8 pF
AVDD
AGND
CLK
C2
1.2 pF
CSample
VCM = AIN+/AIN Common Mode Voltage
AIN
_
+
Figure 32. Equivalent Circuit for Analog Input Pins AIN+ and AIN
The input current pulses required to charge CSample and C2 can be time averaged and the switched capacitor
circuit modelled as an equivalent resistor:
R
IN2 +
1
C
S
f
CLK
where CS is the sum of CSample and C2. This model can be used to approximate the input loading versus source
resistance for high impedance sources.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS1040CDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CDWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CDWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CPW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CPWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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