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參數資料
| 型號： | THS1040CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁數： | 6/36頁 |
| 文件大小： | 751K |
| 代理商： | THS1040CDW |
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THS1040
SLAS290C OCTOBER 2001 REVISED OCTOBER 2004
14
www.ti.com
PRINCIPLES OF OPERATION
functional overview
See the functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation.
Analog inputs AIN+ and AIN are sampled on each rising edge of CLK in a switched capacitor sample and hold
unit, the output of which feeds the ADC core, where analog-to-digital conversion is performed against the ADC
reference voltages REFT and REFB.
Internal or external ADC reference voltage configurations are selected by connecting the MODE pin
appropriately. When MODE = AGND, the user must provide external sources at pins REFB and REFT. When
MODE = AVDD or MODE = AVDD/2, an internal ADC references generator (A2) is enabled which drives the REFT
and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the internal
bandgap reference, or disable A1 and provide their own reference voltage at pin VREF.
On the fourth rising CLK edge following the edge that sampled AIN+ and AIN, the conversion result is output
via data pins D0 to D9. The output buffers can be disabled by pulling pin OE high.
The following sections explain further:
D How signals flow from AIN+ and AIN to the ADC core, and how the reference voltages at REFT and REFB
set the ADC input range and hence the input range at AIN+ and AIN.
D How to set the ADC references REFT and REFB using external sources or the internal reference buffer (A2)
to match the device input range to the input signal.
D How to set the output of the internal bandgap reference (A1) if required.
signal processing chain (sample and hold, ADC)
Figure 20 shows the signal flow through the sample and hold unit to the ADC core.
Sample
and
Hold
X1
ADC
Core
VQ+
VQ
REFT
REFB
AIN+
AIN
Figure 20. Analog Input Signal Flow
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相關代理商/技術參數 |
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| THS1040CDWG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CDWR | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CDWRG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CPW | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1040CPWG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Low Power ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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