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參數資料
| 型號： | THS5651IDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數： | 11/29頁 |
| 文件大小： | 725K |
| 代理商： | THS5651IDW |
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THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
sleep mode
The THS5651 features a power-down mode that turns off the output current and reduces the supply current to
less than 5 mA over the analog supply range of 4.5 V to 5.5 V and temperature range. The power-down mode
is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the THS5651 is enabled if the input is left disconnected. Power-up
and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal
capacitor value of 0.1
F power down takes less than 5 s, and approximately 3 ms to power backup. The
SLEEP mode should not be used when an external control amplifier is used, as shown in Figure 22.
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
offset error
Offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0.
gain error
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D or SINAD)
S/N+D or SINAD is the ratio of the rms value of the output signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in
decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
output compliance range
The maximum and minimum allowable voltage of the output of the DAC, beyond which either saturation of the
output stage or breakdown may occur.
settling time
The time required for the output to settle within a specified error band.
glitch energy
The time integral of the analog value of the glitch transient.
相關PDF資料 |
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| THS5651IPWLE | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28 |
| THS5661AIDWG4 | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| THS5661AIDWRG4 | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| THS5661AIPWRG4 | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| THS5661AIPW | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| THS5651IPW | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| THS5651PW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
| THS5661 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
| THS5661A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT, 125 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
| THS5661ADW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT, 125 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
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