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參數資料
| 型號： | TLC2543QDWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, SOIC-20 |
| 文件頁數： | 25/28頁 |
| 文件大小： | 524K |
| 代理商： | TLC2543QDWREP |
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Operating Characteristics
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
over recommended operating free-air temperature range, V
CC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
EL
Linearity error(2)
See Figure 2
±1
LSB
ED
Differential linearity error
See Figure 2
±1
LSB
EO
Offset error(3)
See Figure 2(4)
±1.5
LSB
EG
Gain error(3)
See Figure 2(4)
±1
LSB
ET
Total unadjusted error(5)
±1.75
LSB
DATA INPUT = 1011
2048
DATA INPUT = 1100
0
DATA INPUT = 1101
4095
t(conv)
Conversion time
8
10
s
10 + total
Total cycle time
I/O CLOCK
tc
s
(access, sample, and conversion)(7)
periods +
td(I/O-EOC)
I/O
tacq
Channel acquisition time (sample)(7)
4
12
CLOCK
periods
Valid time,
tv
DATA OUT remains valid after I/O
See Figure 6
10
ns
CLOCK
↓
Delay time,
td(I/O-DATA)
See Figure 6
150
ns
I/O CLOCK
↓ to DATA OUT valid
Delay time,
td(I/O-EOC)
See Figure 7
1.5
2.2
s
last I/O CLOCK
↓ to EOC↓
Delay time,
td(EOC-DATA)
See Figure 8
100
ns
EOC
↑ to DATA OUT (MSB/LSB)
Enable time,
tPZH, tPZL
See Figure 3
0.7
1.3
s
CS
↓ to DATA OUT (MSB/LSB driven)
Disable time,
tPHZ, tPLZ
See Figure 3
70
150
ns
CS
↑ to DATA OUT (high impedance)
tr(EOC)
Rise time, EOC
See Figure 8
15
50
ns
tf(EOC)
Fall time, EOC
See Figure 7
15
50
ns
tr(bus)
Rise time, data bus
See Figure 6
15
50
ns
tf(bus)
Fall time, data bus
See Figure 6
15
50
ns
Delay time, last I/O CLOCK
↓ to CS↓ to
td(I/O-CS)
5
s
abort conversion(8)
(1)
All typical values are at TA = 25°C.
(2)
Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
(3)
Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain
point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal
midstep value at the offset point.
(4)
Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied
to REF– convert as all zeros (000000000000).
(5)
Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
(6)
Both the input address and the output codes are expressed in positive logic.
(7)
I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7)
(8)
Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at
≤5 s of the
tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5
s and 10 s, the result is uncertain as to whether the
conversion is aborted or the conversion results are valid.
6
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