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參數資料
| 型號： | TLC2578IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁數： | 13/49頁 |
| 文件大小： | 1137K |
| 代理商： | TLC2578IPWRG4 |
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TLC3574, TLC3578, TLC2574, TLC2578
5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL
SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS
SLAS262C OCTOBER 2000 REVISED MAY 2003
20
WWW.TI.COM
start of operation cycle (continued)
CS initiates the operation: If FS is high at the falling edge of CS, the falling edge of CS initiates the operation.
When CS is high, SDO is in high-impedance state, the signals on SDI are ignored, and SCLK is disabled to clock
the serial data. The falling edge of CS resets the internal 4-bit counter and enables SDO, SDI, and SCLK. The
MSB of the input data via SDI, ID(15), is latched at the first falling edge of SCLK following the falling edge of
CS. The MSB of output data from SDO, OD(15), is valid before this SCLK falling edge. This mode works as an
SPI interface when CS is used as SLAVE SELECT (SS). It also can be used as normal DSP interface if CS
connects to the frame sync output of the host DSP. FS must be tied to high in this mode.
FS initiates the operation: If FS is low at the falling edge of CS, the rising edge of FS initiates the operation.
It resets the internal 4-bit counter, and enables SDI, SDO, and SCLK. The ID(15) is latched at the first falling
edge of SCLK following the falling edge of FS. OD(15) is valid before this falling edge of SCLK. This mode is
used to interface the converter with a serial port of the host DSP. The FS of the device is connected to the frame
sync of the host DSP. When several devices are connected to one DSP serial port, CS is used as chip select
to allow the host DSP to access each device individually. If only one converter is used, CS can be tied to low.
After the initiation, the remaining SDI data bits (if any) are shifted in and the remaining bits of SDO (if any) are
shifted out at the rising edge of SCLK. The input data are latched at the falling edge of SCLK, and the output
data are valid before the falling edge of SCLK. After the 4-bit counter reaches 16, the SDO goes to
high-impedance state. The output data from SDO is the previous conversion result in one shot conversion
mode, or the contents in the top of FIFO when FIFO is used (refer to Figure 20).
command period
After the rising edge of FS (FS triggers the operation) or the falling edge of CS (CS triggers the operation), SDI,
SDO, and SCLK are enabled. The first four SCLK clocks form the command period. The four MSBs of input data,
ID[15:12], are shifted in and decoded. These bits represent one of the 4-bit commands from the host, which
defines the required operation (see Table 1). The four MSB of output, OD[15:12], are also shifted out via SDO
during this period.
The commands are SELECT/CONVERSION, WRITE CFR, FIFO READ, and HARDWARE DEFAULT. The
SELECT/CONVERSION command includes SELECT ANALOG INPUT and SELECT TEST commands. All
cause a select/conversion operation. They select the analog signal being converted, and start the
sampling/conversion process after the selection. WRITE CFR causes the configuration operation, which writes
the device configuration information into CFR register. FIFO READ reads the contents in FIFO. Hardware
default mode sets the device into the hardware default mode.
After the command period, the remaining 12 bits of SDI are written into the CFR register to configure the device
if the command is WRITE CFR. Otherwise, these bits are ignored. The configuration is retained in the
autopower-down state. If the SCLK stops (while CS remains low) after the first eight bits are entered, the next
eight bits can be entered after the SCLK resumes. The data on SDI are ignored after the 4-bit counter counts
to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.
The remaining 12 bits of output data are shifted out from SDO if the command is SELECT/CONVERSION or
FIFO READ. Otherwise, the data on SDO must be ignored. In any case, the SDO goes into high-impedance
state after the 4-bit counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever
happens first.
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相關代理商/技術參數 |
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| TLC25L2ACDG4 | 功能描述:運算放大器 - 運放 LiNCMOS Lw Bias RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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