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參數資料
| 型號： | TLC2578IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁數： | 5/49頁 |
| 文件大小： | 1137K |
| 代理商： | TLC2578IPWRG4 |
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TLC3574, TLC3578, TLC2574, TLC2578
5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL
SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS
SLAS262C OCTOBER 2000 REVISED MAY 2003
13
WWW.TI.COM
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted)
SCLK, SDI, SDO, EOC and INT
PARAMETERS
MIN
TYP
MAX
UNIT
tc(1)
Cycle time of SCLK, 25 pF load (see Note 10)
DVDD = 2.7 V
100
ns
tc(1)
Cycle time of SCLK, 25 pF load (see Note 10)
DVDD = 5 V
40
ns
tw(1)
Pulse width of SCLK High, at 25-pF load
40%
60%
tc(1)
tr(1)
Rise time for INT and EOC, at 10-pF load
DVDD = 5 V
6
ns
tr(1)
Rise time for INT and EOC, at 10-pF load
DVDD = 2.7 V
10
ns
tf(1)
Fall time for INT and EOC, at 10-pF load
DVDD = 5 V
6
ns
tf(1)
Fall time for INT and EOC, at 10-pF load
DVDD = 2.7 V
10
ns
tsu(1)
Setup time, new SDI valid (reaches 90% final level) before the falling edge of SCLK, at 25-pF load
6
ns
th(1)
Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at 25-pF load
0
ns
td(1)
Delay time, new SDO valid (reaches 90% of final level) after SCLK rising edge, at 10-pF
DVDD = 5 V
0
10
ns
td(1)
Delay time, new SDO valid (reaches 90% of final level) after SCLK rising edge, at 10-pF
load (see Note 11)
DVDD = 2.7 V
0
23
ns
th(2)
Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF load
0
ns
td(2)
Delay time, delay from the falling edge of 16th SCLK to EOC falling edge, normal sampling, at 10-pF load
0
6
ns
td(3)
Delay time, delay from the falling edge of 16th SCLK to INT falling edge, at 10-pF load (see Notes 11 and 12)
t(conv)
t(conv)+6
ns
NOTES:
9. The minimum pulse width of SCLK high and low is 12.5 ns.
10. Specified by design
11. For normal short sampling, td(3) is the delay from the falling edge of 16th SCLK to the falling edge of INT.
For normal long sampling, td(3) is the delay from the falling edge of 48th SCLK to the falling edge of INT. Conversion time, t(conv),
is equal to 18
× OSC +15 ns (for TLC3574 and TLC3578) or 13 × OSC + 15 ns (for TLC2574 and TLC2578) when using internal
OSC as conversion clock, or 72
× tc(1) + 15 ns (for TLC3574 and TLC3578) or 52 × tc(1) + 15 ns (for TLC2574 and TLC2578) when
external SCLK is conversion clock source.
90%
10%
ID15
OD1
OD0
ID1
Hi-Z
50%
1
16
OD15
Don’t Care
ID0
OR
VIH
VIL
tw(1)
tc(1)
tsu(1)
th(1)
th(2)
td(1)
td(2)
tr(1)
tf(1)
td(3)
Hi-Z
Don’t Care
tf(1)
tr(1)
CS
SCLK
SDI
SDO
EOC
INT
For normal long sampling, td(2) is the delay time of EOC low after the falling edge of 48th SCLK.
For normal long sampling, td(3) is the delay time of INT low after the falling edge of 48th SCLK.
The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiatesthe conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT
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