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參數(shù)資料
| 型號： | TLC3541IDGKG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | GREEN, PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 5/25頁 |
| 文件大小： | 648K |
| 代理商： | TLC3541IDGKG4 |
TLC3541, TLC3545
SLAS345 DECEMBER 2001
13
www.ti.com
PRINCIPLES OF OPERATION
control via pin 1 (CS, DSP interface)
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the
CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC3541
in this configuration, the FS input is tied to VDD.) Enough time should be allowed before the next rising CS edge
so that the conversion cycle is not terminated prematurely.
1
2
3
5
4
6
7
13
14
15
16
1
12
ts
tconv
t(PWRDWN)
SDO Data Is the Result of the Previous Sample
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge
MSB
MSB1
MSB2 MSB3 MSB4 MSB5 MSB6
LSB+2
LSB+1
LSB
LSB1
LSB2
SCLK
CS
SDO
MSB
MSB1
The CS Input Signal Is
Generated by the FS Output
From a TMS320 DSP
24
Figure 16. DSP Cycle Timing Using the CS Input (FS = 1 for TLC3541 only)
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)
Only TLC3541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a
general-purpose I/O pin from the DSP or tied to ground. The FS signal from the DSP is connected directly to
the FS input of the ADC. A rising FS edge releases the MSB to the SDO output. The falling edge on the FS input
while SCLK is high or low initiates the cycle. The CS input should remain low for the entire sampling time plus
4 SCLK decoding time after falling FS (24 falling SCLK edges) and can then be released at any time during the
remainder of the conversion cycle. The optimum DSP interface is achieved when tying CS to ground and using
only the FS input to control the ADC.
tconv
t(PWRDWN)
SDO Data Is the Result of the Previous Sample
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge
1
2
3
5
4
6
14
15
16
1
2
34
ts
MSB
MSB1 MSB2 MSB3 MSB4 MSB5 LSB+1
LSB
LSB1 LSB2
MSB
MSB1 MSB2 MSB3
The MSB Is Presented on the SDO Output After
a Rising Edge on the FS Input.
17
24
The Device Will Go Into the Power Down State After the Conversion Is
Complete. A Falling CS Edge or Rising FS Edge, Whichever Occurs First,
Removes the Device From Power Down.
SCLK
CS
SDO
FS
Figure 17. DSP Cycle Timing Using FS Only (or Using Both CS and FS for TLC3541)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC3541IDGKR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 5V Lo-Pwr 14-Bit 200 KSPS Serial RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC3541IDGKRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 5V Lo-Pwr 14-Bit 200 KSPS Serial RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC3541IDR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 5V Lo-Pwr 14-Bit 200 KSPS Serial RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC3541IDRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 5V Lo-Pwr 14-Bit 200 KSPS Serial RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC3544 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS |
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