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參數資料
型號: TLC3548IDWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝: GREEN, PLASTIC, SOIC-24
文件頁數: 5/44頁
文件大小: 1000K
代理商: TLC3548IDWG4
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CSTART trigger
PARAMETERS
MIN
TYP
MAX
UNIT
td(12)
Delay time, delay from CSTART rising edge to EOC falling
edge, at 10-pF load
0
15
21
ns
tw(4)
Pulse width CSTART low time: tW(L)(CSTART), at 25-pF load
t(sample – ref)+0.4
Note 7
s
td(13)
Delay time, delay from CSTART rising edge to CSTART falling
edge, at 25-pF load
t(conv) +15
Notes 7 and 8
ns
td(14)
Delay time, delay from CSTART rising edge to INT falling edge,
at 10-pF load
t(conv) +15
Notes 7 and 8
t(conv)+21
ns
td(15)
Delay time, delay from CSTART falling edge to INT rising edge,
at 10-pF load
0
6
s
NOTES:
7. The pulse width of CSTART must be not less than the required sampling time. The delay from CSTART rising edge to following
CSTART falling edge must not be less than the required conversion time. The delay from CSTART rising edge to the INT falling edge
is equal to the conversion time.
8. The maximum rate of SCLK is 25 MHz for normal long sampling and 10 MHz for normal short sampling.
t(conv)
OR
tw(4)
td(13)
td(12)
td(14)
td(15)
CSTART
EOC
INT
Extended Sampling
Figure 4. Critical Timing for Extended Sampling (CSTART Trigger)
detailed description
converter
The converters are a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows a
simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling
period. When the conversion process starts, the control logic directs the charge redistribution DAC to add and
subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition.
When balanced, the conversion is complete and the ADC output code is generated.
相關PDF資料
PDF描述
TLC3544IPW 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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相關代理商/技術參數
參數描述
TLC3548IDWR 功能描述:模數轉換器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
TLC3548IDWRG4 功能描述:模數轉換器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
TLC3548IPW 功能描述:模數轉換器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
TLC3548IPW 制造商:Texas Instruments 功能描述:14BIT ADC 200KSPS 3548 TSSOP24 制造商:Texas Instruments 功能描述:14BIT ADC, 200KSPS, 3548, TSSOP24
TLC3548IPWG4 功能描述:模數轉換器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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