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參數(shù)資料
| 型號： | TLC3548IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大小： | 1000K |
| 代理商： | TLC3548IPWRG4 |
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TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO operation (continued)
The device has an 8-level FIFO that can be programmed for different thresholds. An interrupt is sent to the host
after the preprogrammed threshold is reached. The FIFO is used to store conversion results in mode 01, 10,
and 11, from either a fixed channel or a series of channels according to a preprogrammed sweep sequence.
For example, an application may require eight measurements from channel 3. In this case, if the threshold is
set to full, the FIFO is filled with 8 data conversions sequentially taken from channel 3. Another application may
require data from channel 0, 2, 4, and 6 in that order. The threshold is set to 1/2 full and sweep sequence is
selected as 0–2–4–6–0–2–4–6. An interrupt is sent to the host as soon as all four data conversions are in the
FIFO. The FIFO is reset after a power on and a WRITE CFR operation. The contents of the FIFO are retained
during autopower down and software power down.
Powerdown: The device has two power-down modes.
AutoPower-Down Mode: The device enters the autopower-down state at the end of a conversion.
In autopower-down, the power consumption reduces to about 1.8 mA when an internal reference is selected.
The built-in reference is still on to allow the device to resume quickly. The resumption is fast enough for use
between cycles. An active CS, FS, or CSTART resumes the device from power-down state. The power current
is 20
A when an external reference is programmed and SCLK stops.
Software Power-Down Mode: Writing 8000h to the device puts the device into the software power-down state,
and the entire chip (including the built-in reference) is powered down. The power current is reduced to about
20
A if SCLK stops. Deselect CS to save power once the device is in the software power-down mode. An active
CS, FS, or CSTART restores the device. There is no time delay when an external reference is selected.
However, if an internal reference is used, it takes about 20 ms to warm up.
The configuration register is not affected by any of the power-down modes but the sweep operation sequence
must be started over again. All FIFO contents are retained in both power-down modes.
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| TLC3548IPWG4 | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| TLC3548IDWR | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| TLC3548IDWG4 | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
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