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參數資料
| 型號： | TLC3548IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁數： | 23/44頁 |
| 文件大小： | 1000K |
| 代理商： | TLC3548IPWRG4 |
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TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
equivalent input circuit
1.1 k
Max
Ron
MUX
C(sample) = 30 pF Max
VDD
REFM
Ain
Diode Turn on Voltage: 35 V
Equivalent Analog Input Circuit
Equivalent Digital Input Circuit
Digital Input
VDD
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TLC3544
TLC3548
I/O
DESCRIPTION
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
9
10
11
12
9
10
11
12
13
14
15
16
I
Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The
driving source impedance should be less than or equal to 1 k
for normal sampling. For larger
source impedance, use the external hardware conversion start signal CSTART (the low time of
CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling
time.
AGND
14, 18
18, 22
I
Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage
measurements are with respect to AGND.
AVDD
13, 19
17, 23
I
Analog supply voltage
BGAP
17
21
I
Internal bandgap compensation pin. Install compensation capacitors between BGAP and AGND.
0.1
F for external reference; 10 F in parallel with 0.1 F for internal reference.
CS
8
I
Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is
disabled to clock data but works as conversion clock source if programmed. The falling edge of CS
input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from
high-impedance state.
If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave
select (SS) to provide an SPI interface.
If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip
select to allow the host to access the individual converter.
CSTART
20
24
I
External sampling trigger signal, which initiates the sampling from a selected analog input channel
when the device works in extended sampling mode (asynchronous sampling). A high-to-low
transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold
mode and starts the conversion. The low time of the CSTART signal controls the sampling period.
CSTART signal must be long enough for proper sampling. CSTART must stay high long enough
after the low-to-high transition for the conversion to finish maturely. The activation of CSTART is
independent of SCLK and the level of CS and FS. However, the first CSTART cannot be issued
before the rising edge of the 11th SCLK. Tie this terminal to DVDD if not used.
DGND
6
I
Digital ground return for the internal circuitry
DVDD
7
I
Digital supply voltage
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| TLC3544CPWG4 | 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLC3544IDWG4 | 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLC3548IPWG4 | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| TLC3548IDWR | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| TLC3548IDWG4 | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
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