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參數資料
| 型號： | TLC7135CN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP28 |
| 封裝： | GREEN, PLASTIC, DIP-28 |
| 文件頁數： | 16/17頁 |
| 文件大小： | 458K |
| 代理商： | TLC7135CN |
ICL7135C, TLC7135C
4 1/2DIGIT PRECISION
ANALOGTODIGITAL CONVERTERS
SLAS074D DECEMBER 1986 REVISED SEPTEMBER 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
BUSY Output
The BUSY output goes high at the beginning of the signal integrate phase. BUSY remains high until the first
clock pulse after zero crossing or at the end of the measurement cycle when an over-range condition occurs.
It is possible to use the BUSY terminal to serially transmit the conversion result. Serial transmission can be
accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted
output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number of clock
pulses that occur during the deintegrate phase. The conversion result can be obtained by subtracting 10,001
from the total number of clock pulses.
OVER-RANGE Output
When an over-range condition occurs, this terminal goes high after the BUSY signal goes low at the end of the
measurement cycle. As previously noted, the BUSY signal remains high until the end of the measurement cycle
when an over-range condition occurs. The OVER RANGE output goes high at the end of BUSY and goes low
at the beginning of the deintegrate phase in the next measurement cycle.
UNDER-RANGE Output
At the end of the BUSY signal, this terminal goes high when the conversion result is less than or equal to 9%
(count of 1800) of the full-scale range. The UNDER-RANGE output is brought low at the beginning of the signal
integrate phase of the next measurement cycle.
POLARITY Output
The POLARITY output is high for a positive input signal and updates at the beginning of each deintegrate phase.
The polarity output is valid for all inputs including
±0 and OVER RANGE signals.
Digit-Drive (D1, D2, D4 and D5) Outputs
Each digit-drive output (D1 through D5) sequentially goes high for 200 clock pulses. This sequential process
is continuous unless an over-range occurs. When an over-range occurs, all of the digit-drive outputs are blanked
from the end of the strobe sequence until the beginning of the deintegrate phase (when the sequential digit-drive
activation begins again). The blanking activity during an over-range condition can cause the display to flash and
indicate the over-range condition.
BCD Outputs
The BCD bits (B1, B2, B4 and B8) for a given digit are sequentially activated on these outputs. Simultaneously,
the appropriate digit-drive line for the given digit is activated.
System Aspects
Integrating Resistor
The value of the integrating resistor (RINT) is determined by the full-scale input voltage and the output current
of the integrating amplifier. The integrating amplifier can supply 20
A of current with negligible nonlinearity. The
equation for determining the value of this resistor is:
R
INT +
Full Scale Voltage
I
INT
Integrating amplifier current, IINT, from 5 to 40 A yields good results. However, the nominal and recommended
current is 20
A.
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