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參數資料
| 型號： | TLC876MDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數： | 13/22頁 |
| 文件大小： | 339K |
| 代理商： | TLC876MDW |
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
digital inputs and outputs (continued)
Table 1. Output Data Format
AIN VOLTAGE
THREE
DATA
(APPROXIMATE)
STATE
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
> 4 V
0
1
4 V
0
1
3 V
0
1
0
2 V
0
< 2 V
0
X
1
Z
grounding and layout rules
Proper grounding and layout techniques are essential for achieving optimal performance. The analog and digital
grounds on the TLC876 have been separated to optimize the management of return currents in a system. A
printed circuit board (PCB) of at least 4 layers employing a ground plane and power planes should be used with
the TLC876. The use of ground and power planes offers distinct advantages:
D Minimizes the loop area encompassed by a signal and its return path
D Minimizes the impedance associated with ground and power paths
D The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane
These characteristics produce a reduction of electromagnetic interference (EMI) and an overall improvement
in performance.
A properly designed layout prevents noise from coupling onto the input signal. Digital signal traces should not
run parallel with the input signal traces and should be routed away from the input circuitry. The separate analog
and digital grounds should be joined together directly under the TLC876. A solid ground plane under the TLC876
is also acceptable if no significant currents are flowing in that portion of the ground plane under the device. The
general rule for mixed signal layouts is that return currents from digital circuitry should not pass through or under
critical analog circuitry. The system design should minimize the analog lead-in to reduce potential noise pickup.
digital outputs
The DRVDD supply terminal powers each of the on-chip buffers for the output bits (D0–D9) and is a separate
lead from AVDD or DVDD. The output drivers are sized to drive a variety of logic families, while minimizing the
amount of glitch energy generated. A recommended fan-out of one keeps the capacitive load on the output data
drivers below the specified 20 pF level.
For DRVDD = 5 V, the output signal swing can drive both high-speed CMOS and TTL logic families. For TTL,
the on-chip output drivers are designed to support several of the high-speed TTL families (F, AS, S). For
applications where the clock rate is below 20 MSPS, other TTL families are appropriate. For interfacing with
lower voltage CMOS logic, the TLC876 sustains 20 MSPS operation with DRVDD = 3.3 V. Refer to logic family
data sheets for compatibility with the TLC876 digital specifications.
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